JPS5680766A - Teller calculator - Google Patents

Teller calculator

Info

Publication number
JPS5680766A
JPS5680766A JP15688779A JP15688779A JPS5680766A JP S5680766 A JPS5680766 A JP S5680766A JP 15688779 A JP15688779 A JP 15688779A JP 15688779 A JP15688779 A JP 15688779A JP S5680766 A JPS5680766 A JP S5680766A
Authority
JP
Japan
Prior art keywords
verification
titled
memory
key
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15688779A
Other languages
Japanese (ja)
Inventor
Haruyoshi Takayama
Takashi Tsunoda
Tsunenori Soma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15688779A priority Critical patent/JPS5680766A/en
Publication of JPS5680766A publication Critical patent/JPS5680766A/en
Pending legal-status Critical Current

Links

Landscapes

  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)

Abstract

PURPOSE: To prevent erroneous setting and/or erroneous operation by performing calculation regarding a transaction prior to titled selection and then by performing verification while selecting a title.
CONSTITUTION: Prior to titled selection, a central processor performs calculation regarding a preccribed transaction on the basis of a succession of key operations and stores the result in a memory. With verification titled key K7 pushed, a verification arithmetic start signal is generated and supplied to the central processor, which starts verification arithmetic processing. The output of each verification titled key K7 is supplied to a memory address recorder to generate a memory address signal that corresponds to the pushed verification titled key and the signal is outputted to the memory. Next, the verification arithmetic processing regarding the corresponding title is performed by transferring data between the central processor and memory and the processing contents in the verificaton arithmetic processing are supplied to an output device, which print the data on journal paper or a slip.
COPYRIGHT: (C)1981,JPO&Japio
JP15688779A 1979-12-05 1979-12-05 Teller calculator Pending JPS5680766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15688779A JPS5680766A (en) 1979-12-05 1979-12-05 Teller calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15688779A JPS5680766A (en) 1979-12-05 1979-12-05 Teller calculator

Publications (1)

Publication Number Publication Date
JPS5680766A true JPS5680766A (en) 1981-07-02

Family

ID=15637558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15688779A Pending JPS5680766A (en) 1979-12-05 1979-12-05 Teller calculator

Country Status (1)

Country Link
JP (1) JPS5680766A (en)

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