JPS5677963A - Address generating circuit - Google Patents

Address generating circuit

Info

Publication number
JPS5677963A
JPS5677963A JP15543479A JP15543479A JPS5677963A JP S5677963 A JPS5677963 A JP S5677963A JP 15543479 A JP15543479 A JP 15543479A JP 15543479 A JP15543479 A JP 15543479A JP S5677963 A JPS5677963 A JP S5677963A
Authority
JP
Japan
Prior art keywords
address
signal
generating circuit
address generating
subtracted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15543479A
Other languages
Japanese (ja)
Inventor
Asao Yamanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15543479A priority Critical patent/JPS5677963A/en
Publication of JPS5677963A publication Critical patent/JPS5677963A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To perform an operation of the fixed address in a short time, by installing an exclusive address generating circuit corresponding to the arithmetic equation. CONSTITUTION:The specific operation (b-1)c+(d-1)+e is performed by the given plural variables, i.e., the row number (b), the row size (c) and the column number (d) of a matrix plus the head address (e) each, thus producing the address signal (a) to give an access to a memory through the address generating circuit. The signal 1a of the number (b) is subtracted (b-1) by the subtractor 1 and then multiplied by the signal 2a of the row size c7 through the multiplier 2 to obtain (c). On the other hand, the signal 3a of the number (d) is subtracted (d-1) by the substractor 3 to obtain (d-1). Then the above-mentioned (b-1)c, (d-1) and the signal 4a of the head address (e) are added together through the adder 4 to obtain the desired address a=(b-1)c+(d-1)+e. And the normal address is read out to the memory 6 in case the switch 5 is set at 5a.
JP15543479A 1979-11-27 1979-11-27 Address generating circuit Pending JPS5677963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15543479A JPS5677963A (en) 1979-11-27 1979-11-27 Address generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15543479A JPS5677963A (en) 1979-11-27 1979-11-27 Address generating circuit

Publications (1)

Publication Number Publication Date
JPS5677963A true JPS5677963A (en) 1981-06-26

Family

ID=15605932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15543479A Pending JPS5677963A (en) 1979-11-27 1979-11-27 Address generating circuit

Country Status (1)

Country Link
JP (1) JPS5677963A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208173A (en) * 1985-03-12 1986-09-16 Toshiba Corp Image access system
JPS63143646A (en) * 1986-12-05 1988-06-15 Nec Corp Extended index addressing system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4945176A (en) * 1972-09-05 1974-04-30
JPS5282145A (en) * 1975-12-29 1977-07-09 Nec Corp Memory index circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4945176A (en) * 1972-09-05 1974-04-30
JPS5282145A (en) * 1975-12-29 1977-07-09 Nec Corp Memory index circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208173A (en) * 1985-03-12 1986-09-16 Toshiba Corp Image access system
JPS63143646A (en) * 1986-12-05 1988-06-15 Nec Corp Extended index addressing system

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