JPS5663658A - Disk control unit - Google Patents

Disk control unit

Info

Publication number
JPS5663658A
JPS5663658A JP13831479A JP13831479A JPS5663658A JP S5663658 A JPS5663658 A JP S5663658A JP 13831479 A JP13831479 A JP 13831479A JP 13831479 A JP13831479 A JP 13831479A JP S5663658 A JPS5663658 A JP S5663658A
Authority
JP
Japan
Prior art keywords
circuit
checking
case
program
normal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13831479A
Other languages
Japanese (ja)
Inventor
Shigeyuki Kuwabara
Yoshiaki Furuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13831479A priority Critical patent/JPS5663658A/en
Publication of JPS5663658A publication Critical patent/JPS5663658A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To get rid of a fault such as a data error, etc. caused by a malfunction of the checking circuit, and elevate reliability of the system, by always making certain that the checking circuit is normal.
CONSTITUTION: In case when the control circuit 7 is not a checking state, FF10 is reset by the program, and therefore as for the selective circuits 8, 9 the upper terminals 8a, 9a are selected, respectively, and a data signal, etc. are input from the floppy disk driving circuit FD. On the other hand, in case when the circuit 7 is in a checking state, FF10 is set by the program, and therefore as for the circuits 8, 9, the lower terminals 8b, 9b are selected, respectively, and a pseudo signal, etc. are input. In this case, when the program further gives a read command to the control circuit 7, the control signal operates corresponding to the pseudo signal. If the cycle redundancy check of the circuit 7 is normal, the circuit 7 detects a CRC error, reports to the computer MCU, and elevates reliability of the system.
COPYRIGHT: (C)1981,JPO&Japio
JP13831479A 1979-10-26 1979-10-26 Disk control unit Pending JPS5663658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13831479A JPS5663658A (en) 1979-10-26 1979-10-26 Disk control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13831479A JPS5663658A (en) 1979-10-26 1979-10-26 Disk control unit

Publications (1)

Publication Number Publication Date
JPS5663658A true JPS5663658A (en) 1981-05-30

Family

ID=15218988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13831479A Pending JPS5663658A (en) 1979-10-26 1979-10-26 Disk control unit

Country Status (1)

Country Link
JP (1) JPS5663658A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514579U (en) * 1975-06-18 1976-01-13
JPS5117263A (en) * 1974-08-02 1976-02-12 Asahi Dow Ltd Fukugotaino seikeihoho
JPS5161737A (en) * 1974-11-27 1976-05-28 Nippon Electric Co
JPS5253638A (en) * 1975-10-28 1977-04-30 Mitsubishi Electric Corp Mimic equipment of input/output unit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5117263A (en) * 1974-08-02 1976-02-12 Asahi Dow Ltd Fukugotaino seikeihoho
JPS5161737A (en) * 1974-11-27 1976-05-28 Nippon Electric Co
JPS514579U (en) * 1975-06-18 1976-01-13
JPS5253638A (en) * 1975-10-28 1977-04-30 Mitsubishi Electric Corp Mimic equipment of input/output unit

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