JPS5663640A - Display system of electronic apparatus - Google Patents

Display system of electronic apparatus

Info

Publication number
JPS5663640A
JPS5663640A JP13848379A JP13848379A JPS5663640A JP S5663640 A JPS5663640 A JP S5663640A JP 13848379 A JP13848379 A JP 13848379A JP 13848379 A JP13848379 A JP 13848379A JP S5663640 A JPS5663640 A JP S5663640A
Authority
JP
Japan
Prior art keywords
indicator
display
minus
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13848379A
Other languages
Japanese (ja)
Inventor
Takashi Tsunoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP13848379A priority Critical patent/JPS5663640A/en
Publication of JPS5663640A publication Critical patent/JPS5663640A/en
Pending legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To make it possible to exactly display a negative number without decreasing the number of display digits, by applying a blanking signal which turns on and off at a constant period, to the indicator, and displaying the display result by means of flickering, in case when the operation result is minus.
CONSTITUTION: CPU1 executes the arithmetic operation in accordance with operation of the input key, being based on the data stored in RAM2 and RAM3, and stores the obtained operation data in the display buffer 5. The stored data is displayed on the indicator 4. Moreover, CPU1 decodes the address, and inputs it to the clock input of FF7 through the signal line 9. When the operation result is plus, a signal is not generated in the signal line 9, but when it is minus, a clock signal which repeats inversion at a prescribed period appears. An output of FF7 executes blanking to the indicator 4 through the inverter 6, a data displayed on the indicator 4 is displayed by means of flickering at a constant period, and it is shown that the operation result is minus.
COPYRIGHT: (C)1981,JPO&Japio
JP13848379A 1979-10-26 1979-10-26 Display system of electronic apparatus Pending JPS5663640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13848379A JPS5663640A (en) 1979-10-26 1979-10-26 Display system of electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13848379A JPS5663640A (en) 1979-10-26 1979-10-26 Display system of electronic apparatus

Publications (1)

Publication Number Publication Date
JPS5663640A true JPS5663640A (en) 1981-05-30

Family

ID=15223130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13848379A Pending JPS5663640A (en) 1979-10-26 1979-10-26 Display system of electronic apparatus

Country Status (1)

Country Link
JP (1) JPS5663640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6454148U (en) * 1987-09-26 1989-04-04

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6454148U (en) * 1987-09-26 1989-04-04
JPH0537309Y2 (en) * 1987-09-26 1993-09-21

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