JPS5660363A - Ic function test method - Google Patents

Ic function test method

Info

Publication number
JPS5660363A
JPS5660363A JP13834979A JP13834979A JPS5660363A JP S5660363 A JPS5660363 A JP S5660363A JP 13834979 A JP13834979 A JP 13834979A JP 13834979 A JP13834979 A JP 13834979A JP S5660363 A JPS5660363 A JP S5660363A
Authority
JP
Japan
Prior art keywords
ffs
signal
level
circuit blocks
test method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13834979A
Other languages
Japanese (ja)
Inventor
Takashi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP13834979A priority Critical patent/JPS5660363A/en
Publication of JPS5660363A publication Critical patent/JPS5660363A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To test plural circuit blocks having the same function simultaneously to make the test efficient, by subjecting logical outputs of respective circuit blocks, which are obtained by input signals of the concentric level, to analogie addition and by using the addition output level.
CONSTITUTION: Reset signal R, clock signal CL, and signal D are given to FFs D1WDn simultaneously, and output signals q1Wqn of respective FFs are added by operational amplifier A to obtain polarity inversion signal OUT. By detecting the level of this signal OUT, functions of respective FFs can be tested simultaneously.
COPYRIGHT: (C)1981,JPO&Japio
JP13834979A 1979-10-23 1979-10-23 Ic function test method Pending JPS5660363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13834979A JPS5660363A (en) 1979-10-23 1979-10-23 Ic function test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13834979A JPS5660363A (en) 1979-10-23 1979-10-23 Ic function test method

Publications (1)

Publication Number Publication Date
JPS5660363A true JPS5660363A (en) 1981-05-25

Family

ID=15219839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13834979A Pending JPS5660363A (en) 1979-10-23 1979-10-23 Ic function test method

Country Status (1)

Country Link
JP (1) JPS5660363A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199567A (en) * 1975-02-28 1976-09-02 Hitachi Ltd
JPS5335446A (en) * 1976-09-13 1978-04-01 Tektronix Inc Logical analyzer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199567A (en) * 1975-02-28 1976-09-02 Hitachi Ltd
JPS5335446A (en) * 1976-09-13 1978-04-01 Tektronix Inc Logical analyzer

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