JPS5658267U - - Google Patents
Info
- Publication number
- JPS5658267U JPS5658267U JP13911180U JP13911180U JPS5658267U JP S5658267 U JPS5658267 U JP S5658267U JP 13911180 U JP13911180 U JP 13911180U JP 13911180 U JP13911180 U JP 13911180U JP S5658267 U JPS5658267 U JP S5658267U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Freezers Or Refrigerated Showcases (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13911180U JPS62536Y2 (enrdf_load_stackoverflow) | 1980-09-29 | 1980-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13911180U JPS62536Y2 (enrdf_load_stackoverflow) | 1980-09-29 | 1980-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5658267U true JPS5658267U (enrdf_load_stackoverflow) | 1981-05-19 |
| JPS62536Y2 JPS62536Y2 (enrdf_load_stackoverflow) | 1987-01-08 |
Family
ID=29370461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13911180U Expired JPS62536Y2 (enrdf_load_stackoverflow) | 1980-09-29 | 1980-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62536Y2 (enrdf_load_stackoverflow) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7582519B2 (en) | 2002-11-05 | 2009-09-01 | Fairchild Semiconductor Corporation | Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction |
| US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
| US9484451B2 (en) | 2007-10-05 | 2016-11-01 | Vishay-Siliconix | MOSFET active area and edge termination area charge balance |
| US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
-
1980
- 1980-09-29 JP JP13911180U patent/JPS62536Y2/ja not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7582519B2 (en) | 2002-11-05 | 2009-09-01 | Fairchild Semiconductor Corporation | Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction |
| US9484451B2 (en) | 2007-10-05 | 2016-11-01 | Vishay-Siliconix | MOSFET active area and edge termination area charge balance |
| US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
| US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62536Y2 (enrdf_load_stackoverflow) | 1987-01-08 |