JPS5658186A - Data processing unit for designating virtual memory address - Google Patents

Data processing unit for designating virtual memory address

Info

Publication number
JPS5658186A
JPS5658186A JP13572580A JP13572580A JPS5658186A JP S5658186 A JPS5658186 A JP S5658186A JP 13572580 A JP13572580 A JP 13572580A JP 13572580 A JP13572580 A JP 13572580A JP S5658186 A JPS5658186 A JP S5658186A
Authority
JP
Japan
Prior art keywords
processing unit
data processing
memory address
virtual memory
designating virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13572580A
Other languages
English (en)
Inventor
Fuaiseru Uorufugangu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPS5658186A publication Critical patent/JPS5658186A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
JP13572580A 1979-09-28 1980-09-29 Data processing unit for designating virtual memory address Pending JPS5658186A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2939411A DE2939411C2 (de) 1979-09-28 1979-09-28 Datenverarbeitungsanlage mit virtueller Speicheradressierung

Publications (1)

Publication Number Publication Date
JPS5658186A true JPS5658186A (en) 1981-05-21

Family

ID=6082156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13572580A Pending JPS5658186A (en) 1979-09-28 1980-09-29 Data processing unit for designating virtual memory address

Country Status (4)

Country Link
US (1) US4395754A (ja)
EP (1) EP0026459A3 (ja)
JP (1) JPS5658186A (ja)
DE (1) DE2939411C2 (ja)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3138973A1 (de) * 1981-09-30 1983-04-21 Siemens AG, 1000 Berlin und 8000 München Vlsi-gerechter onchip mikroprozessorcachespeicher und verfahren zu seinem betrieb
US4473878A (en) * 1981-11-23 1984-09-25 Motorola, Inc. Memory management unit
DE3300223A1 (de) * 1983-01-05 1984-07-05 Siemens AG, 1000 Berlin und 8000 München Anordnung zur umwandlung einer virtuellen adresse in eine physikalische adresse fuer einen in seiten organisierten arbeitsspeicher einer datenverarbeitungsanlage
EP0124799B1 (en) * 1983-04-13 1990-10-31 Nec Corporation Memory access arrangement in a data processing system
US4724518A (en) * 1983-07-29 1988-02-09 Hewlett-Packard Company Odd/even storage in cache memory
US4682281A (en) * 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
US4965720A (en) * 1988-07-18 1990-10-23 International Business Machines Corporation Directed address generation for virtual-address data processors
US5111423A (en) * 1988-07-21 1992-05-05 Altera Corporation Programmable interface for computer system peripheral circuit card
US5434990A (en) * 1990-08-06 1995-07-18 Ncr Corporation Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
US5483644A (en) * 1993-04-15 1996-01-09 Vlsi Technology, Inc. Method for increasing cacheable address space in a second level cache
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US6016535A (en) * 1995-10-11 2000-01-18 Citrix Systems, Inc. Method for dynamically and efficiently caching objects by subdividing cache memory blocks into equally-sized sub-blocks
US6081623A (en) * 1995-10-11 2000-06-27 Citrix Systems, Inc. Method for lossless bandwidth compression of a series of glyphs
US6057857A (en) 1996-06-12 2000-05-02 Citrix Systems, Inc. Method for the lossless compression of lines in a distributed computer system
US6397297B1 (en) * 1999-12-30 2002-05-28 Intel Corp. Dual cache with multiple interconnection operation modes
WO2001093525A2 (en) 2000-05-26 2001-12-06 Citrix Systems, Inc. Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism
US8423673B2 (en) 2005-03-14 2013-04-16 Citrix Systems, Inc. Method and apparatus for updating a graphical display in a distributed processing environment using compression
US8171169B2 (en) * 2005-03-14 2012-05-01 Citrix Systems, Inc. Method and apparatus for updating a graphical display in a distributed processing environment
US7831742B2 (en) * 2007-08-10 2010-11-09 Qimonda Ag Method and device for enumeration
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5415620A (en) * 1977-07-06 1979-02-05 Nec Corp Buffer memory unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761881A (en) * 1971-06-30 1973-09-25 Ibm Translation storage scheme for virtual memory system
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
JPS5615066B2 (ja) * 1974-06-13 1981-04-08
DE2605617A1 (de) * 1976-02-12 1977-08-18 Siemens Ag Schaltungsanordnung zum adressieren von daten

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5415620A (en) * 1977-07-06 1979-02-05 Nec Corp Buffer memory unit

Also Published As

Publication number Publication date
DE2939411C2 (de) 1982-09-02
EP0026459A3 (de) 1982-09-15
EP0026459A2 (de) 1981-04-08
DE2939411A1 (de) 1981-04-02
US4395754A (en) 1983-07-26

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