JPS5654145A - Data transmission system between processors - Google Patents

Data transmission system between processors

Info

Publication number
JPS5654145A
JPS5654145A JP13101779A JP13101779A JPS5654145A JP S5654145 A JPS5654145 A JP S5654145A JP 13101779 A JP13101779 A JP 13101779A JP 13101779 A JP13101779 A JP 13101779A JP S5654145 A JPS5654145 A JP S5654145A
Authority
JP
Japan
Prior art keywords
terminal
processors
data transfer
data link
master station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13101779A
Other languages
Japanese (ja)
Inventor
Mitsuo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13101779A priority Critical patent/JPS5654145A/en
Publication of JPS5654145A publication Critical patent/JPS5654145A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Abstract

PURPOSE:To decrease the data transfer time, by direct data transfer among terminal stations. CONSTITUTION:In the data transfer among processors 2n1 having each high level data link control circuit 2n0, the master station selecting circuit 300 selects one terminal station transmitting the data link usage request signal among all the terminal stations, and the selected terminal station performs operation with a data link usage permission signal from the master station selection circuit and changes the fixed address to an upper rank address. Thus, the terminal station is changed into the master station.
JP13101779A 1979-10-11 1979-10-11 Data transmission system between processors Pending JPS5654145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13101779A JPS5654145A (en) 1979-10-11 1979-10-11 Data transmission system between processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13101779A JPS5654145A (en) 1979-10-11 1979-10-11 Data transmission system between processors

Publications (1)

Publication Number Publication Date
JPS5654145A true JPS5654145A (en) 1981-05-14

Family

ID=15048038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13101779A Pending JPS5654145A (en) 1979-10-11 1979-10-11 Data transmission system between processors

Country Status (1)

Country Link
JP (1) JPS5654145A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285638A (en) * 1985-06-13 1986-12-16 New Japan Radio Co Ltd Straight beam microwave tube
JPS62162159A (en) * 1986-01-13 1987-07-18 Hitachi Ltd Control method for masterless serial bus occupation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285638A (en) * 1985-06-13 1986-12-16 New Japan Radio Co Ltd Straight beam microwave tube
JPS62162159A (en) * 1986-01-13 1987-07-18 Hitachi Ltd Control method for masterless serial bus occupation

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