JPS5654128A - Timing unit - Google Patents
Timing unitInfo
- Publication number
- JPS5654128A JPS5654128A JP13057780A JP13057780A JPS5654128A JP S5654128 A JPS5654128 A JP S5654128A JP 13057780 A JP13057780 A JP 13057780A JP 13057780 A JP13057780 A JP 13057780A JP S5654128 A JPS5654128 A JP S5654128A
- Authority
- JP
- Japan
- Prior art keywords
- timing unit
- timing
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19792938043 DE2938043A1 (en) | 1979-09-20 | 1979-09-20 | High accuracy redundant clock signal supplying circuit - uses majority decision circuits and several regulated clock generators |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5654128A true JPS5654128A (en) | 1981-05-14 |
Family
ID=6081364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13057780A Pending JPS5654128A (en) | 1979-09-20 | 1980-09-19 | Timing unit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS5654128A (en) |
DE (1) | DE2938043A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU549343B2 (en) * | 1981-06-08 | 1986-01-23 | British Telecommunications Public Limited Company | Phase locking |
FR2546691B1 (en) * | 1983-05-27 | 1985-07-05 | Cit Alcatel | TIME BASE |
DE3924907A1 (en) * | 1989-07-27 | 1991-01-31 | Siemens Ag | REDUNDANT CLOCK ARRANGEMENT |
FI87867C (en) * | 1991-01-09 | 1993-02-25 | Telenokia Oy | Oscillator unit with a guaranteed frequency stability |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1238582A (en) * | 1969-08-15 | 1971-07-07 |
-
1979
- 1979-09-20 DE DE19792938043 patent/DE2938043A1/en active Granted
-
1980
- 1980-09-19 JP JP13057780A patent/JPS5654128A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2938043A1 (en) | 1981-04-09 |
DE2938043C2 (en) | 1988-07-14 |
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