JPS5653222B2 - - Google Patents
Info
- Publication number
- JPS5653222B2 JPS5653222B2 JP15291076A JP15291076A JPS5653222B2 JP S5653222 B2 JPS5653222 B2 JP S5653222B2 JP 15291076 A JP15291076 A JP 15291076A JP 15291076 A JP15291076 A JP 15291076A JP S5653222 B2 JPS5653222 B2 JP S5653222B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15291076A JPS5378065A (en) | 1976-12-21 | 1976-12-21 | Method of connecting external terminal to ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15291076A JPS5378065A (en) | 1976-12-21 | 1976-12-21 | Method of connecting external terminal to ic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5378065A JPS5378065A (en) | 1978-07-11 |
| JPS5653222B2 true JPS5653222B2 (enrdf_load_stackoverflow) | 1981-12-17 |
Family
ID=15550802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15291076A Granted JPS5378065A (en) | 1976-12-21 | 1976-12-21 | Method of connecting external terminal to ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5378065A (enrdf_load_stackoverflow) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274097A (ja) * | 1988-09-09 | 1990-03-14 | Fujitsu Ltd | 電子部品のリード端子の半田付け方法 |
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1976
- 1976-12-21 JP JP15291076A patent/JPS5378065A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5378065A (en) | 1978-07-11 |