JPS5651073A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5651073A
JPS5651073A JP12746979A JP12746979A JPS5651073A JP S5651073 A JPS5651073 A JP S5651073A JP 12746979 A JP12746979 A JP 12746979A JP 12746979 A JP12746979 A JP 12746979A JP S5651073 A JPS5651073 A JP S5651073A
Authority
JP
Japan
Prior art keywords
adjacent
cells
memory cell
odd number
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12746979A
Other languages
Japanese (ja)
Inventor
Tsutomu Ishikawa
Kazumitsu Matsuzawa
Noboru Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12746979A priority Critical patent/JPS5651073A/en
Publication of JPS5651073A publication Critical patent/JPS5651073A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to detect the interference among the adjacent cells of rows and columns even in parity pattern test, by splitting the binary address of memory cell arrays of matrix arrangement so that the number of 1's is divided into two groups as an even and an odd number. CONSTITUTION:Depending on the specified combination of inversion circuits 2... and logical product circuits 4..., the number of 1's forming the binary signal of row and column addresses of matrix arrangement memory cells is changed into an even number and an odd number every adjacent row and column. Accordingly, the memory cell E selected when the number of 1's in binary notation of the entire address is an even number, and the memory cell O selected when it is an odd number, constitute checker board shape. In the test by parity pattern, since opposite data as the checker board are written in the cells, different data are written in similarly among the adjacent memory cells. As a result, the detection of interference among adjacent memories can simultaneously be made with the parity check.
JP12746979A 1979-10-03 1979-10-03 Memory unit Pending JPS5651073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12746979A JPS5651073A (en) 1979-10-03 1979-10-03 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12746979A JPS5651073A (en) 1979-10-03 1979-10-03 Memory unit

Publications (1)

Publication Number Publication Date
JPS5651073A true JPS5651073A (en) 1981-05-08

Family

ID=14960690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12746979A Pending JPS5651073A (en) 1979-10-03 1979-10-03 Memory unit

Country Status (1)

Country Link
JP (1) JPS5651073A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215100A (en) * 1983-05-19 1984-12-04 Matsushita Refrig Co Check method of semiconductor memory
JPH0773665A (en) * 1993-06-16 1995-03-17 Nec Corp Method of testing semiconductor memory device
US5631870A (en) * 1994-09-13 1997-05-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory
KR100387014B1 (en) * 2000-05-19 2003-06-12 가부시키가이샤 아드반테스트 Semiconductor testing device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215100A (en) * 1983-05-19 1984-12-04 Matsushita Refrig Co Check method of semiconductor memory
JPH0773665A (en) * 1993-06-16 1995-03-17 Nec Corp Method of testing semiconductor memory device
US5631870A (en) * 1994-09-13 1997-05-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory
US5808949A (en) * 1994-09-13 1998-09-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory
US5963491A (en) * 1994-09-13 1999-10-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory
KR100387014B1 (en) * 2000-05-19 2003-06-12 가부시키가이샤 아드반테스트 Semiconductor testing device

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