JPS56501824A - - Google Patents

Info

Publication number
JPS56501824A
JPS56501824A JP81500445A JP50044581A JPS56501824A JP S56501824 A JPS56501824 A JP S56501824A JP 81500445 A JP81500445 A JP 81500445A JP 50044581 A JP50044581 A JP 50044581A JP S56501824 A JPS56501824 A JP S56501824A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP81500445A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS56501824A publication Critical patent/JPS56501824A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP81500445A 1979-12-26 1980-12-22 Pending JPS56501824A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/106,453 US4308619A (en) 1979-12-26 1979-12-26 Apparatus and methods for synchronizing a digital receiver
PCT/US1980/001694 WO1981001928A1 (en) 1979-12-26 1980-12-22 Apparatus for synchronizing a digital receiver

Publications (1)

Publication Number Publication Date
JPS56501824A true JPS56501824A (ja) 1981-12-10

Family

ID=22311489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP81500445A Pending JPS56501824A (ja) 1979-12-26 1980-12-22

Country Status (4)

Country Link
US (1) US4308619A (ja)
EP (1) EP0042416A4 (ja)
JP (1) JPS56501824A (ja)
WO (1) WO1981001928A1 (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE439083B (sv) * 1981-11-30 1985-05-28 Ellemtel Utvecklings Ab Sett att bringa en oscillator i fas med en inkommande signal jemte anordning for genomforandet av settet
US4569063A (en) * 1983-06-22 1986-02-04 Gte Automatic Electric Incorporated Digital phase locking arrangement for synchronizing digital span data
MX157636A (es) * 1984-01-03 1988-12-07 Motorola Inc Mejoras en circuito de sincronizacion de fase digital de frecuencia multiple
US4573017A (en) * 1984-01-03 1986-02-25 Motorola, Inc. Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop
US4745391A (en) * 1987-02-26 1988-05-17 General Electric Company Method of, and apparatus for, information communication via a power line conductor
US4837779A (en) * 1988-04-12 1989-06-06 Dual-Lite Manufacturing, Inc. Communicator and communication method and system
US5105108A (en) * 1990-11-14 1992-04-14 Zenith Electronics Corporation Delay circuit with phase locked loop control
DE4138543A1 (de) * 1991-11-23 1993-05-27 Philips Patentverwaltung Digitaler phasenregelkreis
US5682112A (en) * 1994-05-18 1997-10-28 Nec Corporation Phase locked loop control apparatus
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
US5986574A (en) * 1997-10-16 1999-11-16 Peco Energy Company System and method for communication between remote locations
FR2783986B1 (fr) * 1998-09-30 2000-12-15 St Microelectronics Sa Procede et dispositif de generation d'un signal d'horloge
US6771712B2 (en) * 2001-07-27 2004-08-03 The Pulsar Network, Inc. System for extracting a clock signal and a digital data signal from a modulated carrier signal in a receiver
JP4633796B2 (ja) * 2004-07-15 2011-02-16 トムソン ライセンシング キャリア再生を向上させるシステム及び方法
US10972108B1 (en) * 2019-12-06 2021-04-06 Qualcomm Incorporated Systems and methods for reduction of in-phase and quadrature-phase (IQ) clock skew

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671776A (en) * 1970-05-01 1972-06-20 Xerox Corp Digital signal synchronizing system
BE786798A (fr) * 1971-07-29 1973-01-29 Int Standard Electric Corp Boucle d'asservissement en phase pour demultiplexeur de signauxmic
US3865981A (en) * 1973-07-16 1975-02-11 Odetics Inc Clock signal assurance in digital data communication systems
US3973087A (en) * 1974-12-05 1976-08-03 General Electric Company Signal repeater for power line access data system
US3973240A (en) * 1974-12-05 1976-08-03 General Electric Company Power line access data system
US3944723A (en) * 1974-12-05 1976-03-16 General Electric Company Station for power line access data system
US4135181A (en) * 1976-01-30 1979-01-16 General Electric Company Automatic remote meter reading and control system
US4032858A (en) * 1976-06-03 1977-06-28 Motorola, Inc. Automatic frequency control system
US4109204A (en) * 1976-12-29 1978-08-22 General Electric Company Apparatus and method for wideband communication with suppression of harmonic interference
US4161720A (en) * 1977-05-23 1979-07-17 General Electric Company Meter terminal unit for use in automatic remote meter reading and control system
US4119926A (en) * 1977-12-08 1978-10-10 Nasa Apparatus and method for stabilized phase detection for binary signal tracking loops
DE2824137C2 (de) * 1978-06-02 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Einrichtung zur Phasensynchronisation

Also Published As

Publication number Publication date
EP0042416A4 (en) 1982-04-29
US4308619A (en) 1981-12-29
WO1981001928A1 (en) 1981-07-09
EP0042416A1 (en) 1981-12-30

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