JPS56501586A - - Google Patents

Info

Publication number
JPS56501586A
JPS56501586A JP81500500A JP50050081A JPS56501586A JP S56501586 A JPS56501586 A JP S56501586A JP 81500500 A JP81500500 A JP 81500500A JP 50050081 A JP50050081 A JP 50050081A JP S56501586 A JPS56501586 A JP S56501586A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP81500500A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS56501586A publication Critical patent/JPS56501586A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10W20/01—
    • H10W20/43—

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Catalysts (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP81500500A 1979-12-28 1980-10-15 Pending JPS56501586A (en:Method)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/108,289 US4319396A (en) 1979-12-28 1979-12-28 Method for fabricating IGFET integrated circuits
PCT/US1980/001355 WO1981001913A1 (en) 1979-12-28 1980-10-15 Method for fabricating igfet integrated circuits

Publications (1)

Publication Number Publication Date
JPS56501586A true JPS56501586A (en:Method) 1981-10-29

Family

ID=22321345

Family Applications (2)

Application Number Title Priority Date Filing Date
JP81500500A Pending JPS56501586A (en:Method) 1979-12-28 1980-10-15
JP56500500A Expired - Lifetime JPH0544191B2 (en:Method) 1979-12-28 1980-10-15

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP56500500A Expired - Lifetime JPH0544191B2 (en:Method) 1979-12-28 1980-10-15

Country Status (6)

Country Link
US (1) US4319396A (en:Method)
EP (1) EP0042420B1 (en:Method)
JP (2) JPS56501586A (en:Method)
CA (1) CA1143072A (en:Method)
DE (1) DE3072027D1 (en:Method)
WO (1) WO1981001913A1 (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008026284A1 (en) * 2006-08-31 2008-03-06 Fujitsu Limited Logic circuit

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5165086A (en) * 1985-02-20 1992-11-17 Hitachi, Ltd. Microprocessor chip using two-level metal lines technology
US4742019A (en) * 1985-10-30 1988-05-03 International Business Machines Corporation Method for forming aligned interconnections between logic stages
US5119313A (en) * 1987-08-04 1992-06-02 Texas Instruments Incorporated Comprehensive logic circuit layout system
JPH06314692A (ja) * 1993-04-27 1994-11-08 Intel Corp 集積回路におけるビア／接点被覆範囲を改善する方法
US5358886A (en) * 1993-07-01 1994-10-25 Lsi Logic Corporation Method of making integrated circuit structure with programmable conductive electrode/interconnect material
US5874754A (en) * 1993-07-01 1999-02-23 Lsi Logic Corporation Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates
US5440154A (en) * 1993-07-01 1995-08-08 Lsi Logic Corporation Non-rectangular MOS device configurations for gate array type integrated circuits
EP0685881A1 (en) * 1994-05-31 1995-12-06 AT&T Corp. Linewidth control apparatus and method
US5696943A (en) * 1995-07-27 1997-12-09 Advanced Micro Devices, Inc. Method and apparatus for quick and reliable design modification on silicon
US6077308A (en) * 1997-08-21 2000-06-20 Micron Technology, Inc. Creating layout for integrated circuit structures
US6600341B2 (en) 2001-05-01 2003-07-29 Lattice Semiconductor Corp. Integrated circuit and associated design method using spare gate islands
US6814296B2 (en) 2001-05-01 2004-11-09 Lattice Semiconductor Corp. Integrated circuit and associated design method with antenna error control using spare gates
US7183623B2 (en) * 2001-10-02 2007-02-27 Agere Systems Inc. Trimmed integrated circuits with fuse circuits
US6747445B2 (en) 2001-10-31 2004-06-08 Agere Systems Inc. Stress migration test structure and method therefor
US6902957B2 (en) * 2003-05-05 2005-06-07 Faraday Technology Corp. Metal programmable integrated circuit capable of utilizing a plurality of clock sources and capable of eliminating clock skew

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4964385A (en:Method) * 1972-06-30 1974-06-21
JPS51147982A (en) * 1975-06-13 1976-12-18 Nec Corp Integrated circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3475621A (en) * 1967-03-23 1969-10-28 Ibm Standardized high-density integrated circuit arrangement and method
DE1762759B1 (de) * 1968-08-20 1970-08-20 Philips Patentverwaltung Monolithisch integrierte Schaltung zur Umsetzung einer Information aus einem Code in einen anderen
GB1357515A (en) * 1972-03-10 1974-06-26 Matsushita Electronics Corp Method for manufacturing an mos integrated circuit
US3747200A (en) * 1972-03-31 1973-07-24 Motorola Inc Integrated circuit fabrication method
JPS5947464B2 (ja) * 1974-09-11 1984-11-19 株式会社日立製作所 半導体装置
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
GB1575741A (en) * 1977-01-17 1980-09-24 Philips Electronic Associated Integrated circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4964385A (en:Method) * 1972-06-30 1974-06-21
JPS51147982A (en) * 1975-06-13 1976-12-18 Nec Corp Integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008026284A1 (en) * 2006-08-31 2008-03-06 Fujitsu Limited Logic circuit

Also Published As

Publication number Publication date
EP0042420B1 (en) 1987-09-09
EP0042420A4 (en) 1984-11-22
JPS56500046A (en:Method) 1981-01-16
JPH0544191B2 (en:Method) 1993-07-05
WO1981001913A1 (en) 1981-07-09
EP0042420A1 (en) 1981-12-30
US4319396A (en) 1982-03-16
DE3072027D1 (en) 1987-10-15
CA1143072A (en) 1983-03-15

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