JPS56500046A - - Google Patents
Info
- Publication number
- JPS56500046A JPS56500046A JP50050080A JP50050080A JPS56500046A JP S56500046 A JPS56500046 A JP S56500046A JP 50050080 A JP50050080 A JP 50050080A JP 50050080 A JP50050080 A JP 50050080A JP S56500046 A JPS56500046 A JP S56500046A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H10W20/01—
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- H10W20/43—
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Catalysts (AREA)
- Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/108,289 US4319396A (en) | 1979-12-28 | 1979-12-28 | Method for fabricating IGFET integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56500046A true JPS56500046A (enExample) | 1981-01-16 |
| JPH0544191B2 JPH0544191B2 (enExample) | 1993-07-05 |
Family
ID=22321345
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP81500500A Pending JPS56501586A (enExample) | 1979-12-28 | 1980-10-15 | |
| JP56500500A Expired - Lifetime JPH0544191B2 (enExample) | 1979-12-28 | 1980-10-15 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP81500500A Pending JPS56501586A (enExample) | 1979-12-28 | 1980-10-15 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4319396A (enExample) |
| EP (1) | EP0042420B1 (enExample) |
| JP (2) | JPS56501586A (enExample) |
| CA (1) | CA1143072A (enExample) |
| DE (1) | DE3072027D1 (enExample) |
| WO (1) | WO1981001913A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5165086A (en) * | 1985-02-20 | 1992-11-17 | Hitachi, Ltd. | Microprocessor chip using two-level metal lines technology |
| US4742019A (en) * | 1985-10-30 | 1988-05-03 | International Business Machines Corporation | Method for forming aligned interconnections between logic stages |
| US5119313A (en) * | 1987-08-04 | 1992-06-02 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
| JPH06314692A (ja) * | 1993-04-27 | 1994-11-08 | Intel Corp | 集積回路におけるビア／接点被覆範囲を改善する方法 |
| US5874754A (en) * | 1993-07-01 | 1999-02-23 | Lsi Logic Corporation | Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates |
| US5440154A (en) * | 1993-07-01 | 1995-08-08 | Lsi Logic Corporation | Non-rectangular MOS device configurations for gate array type integrated circuits |
| US5358886A (en) * | 1993-07-01 | 1994-10-25 | Lsi Logic Corporation | Method of making integrated circuit structure with programmable conductive electrode/interconnect material |
| EP0685881A1 (en) * | 1994-05-31 | 1995-12-06 | AT&T Corp. | Linewidth control apparatus and method |
| US5696943A (en) * | 1995-07-27 | 1997-12-09 | Advanced Micro Devices, Inc. | Method and apparatus for quick and reliable design modification on silicon |
| US6077308A (en) * | 1997-08-21 | 2000-06-20 | Micron Technology, Inc. | Creating layout for integrated circuit structures |
| US6600341B2 (en) | 2001-05-01 | 2003-07-29 | Lattice Semiconductor Corp. | Integrated circuit and associated design method using spare gate islands |
| US6814296B2 (en) | 2001-05-01 | 2004-11-09 | Lattice Semiconductor Corp. | Integrated circuit and associated design method with antenna error control using spare gates |
| US7183623B2 (en) * | 2001-10-02 | 2007-02-27 | Agere Systems Inc. | Trimmed integrated circuits with fuse circuits |
| US6747445B2 (en) | 2001-10-31 | 2004-06-08 | Agere Systems Inc. | Stress migration test structure and method therefor |
| US6902957B2 (en) * | 2003-05-05 | 2005-06-07 | Faraday Technology Corp. | Metal programmable integrated circuit capable of utilizing a plurality of clock sources and capable of eliminating clock skew |
| WO2008026284A1 (en) * | 2006-08-31 | 2008-03-06 | Fujitsu Limited | Logic circuit |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3475621A (en) * | 1967-03-23 | 1969-10-28 | Ibm | Standardized high-density integrated circuit arrangement and method |
| DE1762759B1 (de) * | 1968-08-20 | 1970-08-20 | Philips Patentverwaltung | Monolithisch integrierte Schaltung zur Umsetzung einer Information aus einem Code in einen anderen |
| GB1357515A (en) * | 1972-03-10 | 1974-06-26 | Matsushita Electronics Corp | Method for manufacturing an mos integrated circuit |
| US3747200A (en) * | 1972-03-31 | 1973-07-24 | Motorola Inc | Integrated circuit fabrication method |
| FR2198267B1 (enExample) * | 1972-06-30 | 1977-07-29 | Ibm | |
| JPS5947464B2 (ja) * | 1974-09-11 | 1984-11-19 | 株式会社日立製作所 | 半導体装置 |
| JPS51147982A (en) * | 1975-06-13 | 1976-12-18 | Nec Corp | Integrated circuit |
| US4125854A (en) * | 1976-12-02 | 1978-11-14 | Mostek Corporation | Symmetrical cell layout for static RAM |
| GB1575741A (en) * | 1977-01-17 | 1980-09-24 | Philips Electronic Associated | Integrated circuits |
-
1979
- 1979-12-28 US US06/108,289 patent/US4319396A/en not_active Expired - Lifetime
-
1980
- 1980-10-15 DE DE8181900279T patent/DE3072027D1/de not_active Expired
- 1980-10-15 JP JP81500500A patent/JPS56501586A/ja active Pending
- 1980-10-15 WO PCT/US1980/001355 patent/WO1981001913A1/en not_active Ceased
- 1980-10-15 EP EP81900279A patent/EP0042420B1/en not_active Expired
- 1980-10-15 JP JP56500500A patent/JPH0544191B2/ja not_active Expired - Lifetime
- 1980-10-22 CA CA000363014A patent/CA1143072A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| WO1981001913A1 (en) | 1981-07-09 |
| JPS56501586A (enExample) | 1981-10-29 |
| EP0042420A4 (en) | 1984-11-22 |
| JPH0544191B2 (enExample) | 1993-07-05 |
| EP0042420A1 (en) | 1981-12-30 |
| CA1143072A (en) | 1983-03-15 |
| EP0042420B1 (en) | 1987-09-09 |
| US4319396A (en) | 1982-03-16 |
| DE3072027D1 (en) | 1987-10-15 |