JPS564955A - Timing extracting circuit - Google Patents

Timing extracting circuit

Info

Publication number
JPS564955A
JPS564955A JP7988179A JP7988179A JPS564955A JP S564955 A JPS564955 A JP S564955A JP 7988179 A JP7988179 A JP 7988179A JP 7988179 A JP7988179 A JP 7988179A JP S564955 A JPS564955 A JP S564955A
Authority
JP
Japan
Prior art keywords
constant
gain
data
amplifier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7988179A
Other languages
Japanese (ja)
Inventor
Youshirou Mino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7988179A priority Critical patent/JPS564955A/en
Publication of JPS564955A publication Critical patent/JPS564955A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make it possible to design PLL unconditionally by keeping a loop gain constant without reference to a mark rate by integrating RZ(return to zero) input data and then by controlling the gain of a DC amplifier with the integral output voltage. CONSTITUTION:With the output of integration of RZ data from input 1, the gain of variable gain DC amplifier 8 is controlled at input data integrating circuit 7. Then, circuit 7 generates control voltage E=A.P (A: constant) proportional to mark rate P of the data and in terms of DC gain KT of amplifier 8 controlled with this control voltage E we have KT=B/E (B: constant). This constitution keeps constant loop gain K=(B.C)/A (C: constant) of the PLL circuit, and loop gain K becomes constant without reference to mark rate P of data.
JP7988179A 1979-06-22 1979-06-22 Timing extracting circuit Pending JPS564955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7988179A JPS564955A (en) 1979-06-22 1979-06-22 Timing extracting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7988179A JPS564955A (en) 1979-06-22 1979-06-22 Timing extracting circuit

Publications (1)

Publication Number Publication Date
JPS564955A true JPS564955A (en) 1981-01-19

Family

ID=13702577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7988179A Pending JPS564955A (en) 1979-06-22 1979-06-22 Timing extracting circuit

Country Status (1)

Country Link
JP (1) JPS564955A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02139983A (en) * 1988-11-21 1990-05-29 Nec Corp Semiconductor laser driver circuit
WO2002069555A1 (en) * 2001-02-23 2002-09-06 Anritsu Corporation Instrument for measuring characteristic of data transmission system with high accuracy and clock reproducing circuit used therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02139983A (en) * 1988-11-21 1990-05-29 Nec Corp Semiconductor laser driver circuit
JP2734026B2 (en) * 1988-11-21 1998-03-30 日本電気株式会社 Semiconductor laser drive circuit
WO2002069555A1 (en) * 2001-02-23 2002-09-06 Anritsu Corporation Instrument for measuring characteristic of data transmission system with high accuracy and clock reproducing circuit used therefor
US6782353B2 (en) 2001-02-23 2004-08-24 Anritsu Corporation Instrument for measuring characteristic of data transmission system with high accuracy and clock reproducing circuit used therefor

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