JPS5647827A - Output signal controlling circuit of microcomputer system - Google Patents

Output signal controlling circuit of microcomputer system

Info

Publication number
JPS5647827A
JPS5647827A JP12389279A JP12389279A JPS5647827A JP S5647827 A JPS5647827 A JP S5647827A JP 12389279 A JP12389279 A JP 12389279A JP 12389279 A JP12389279 A JP 12389279A JP S5647827 A JPS5647827 A JP S5647827A
Authority
JP
Japan
Prior art keywords
output signal
buffer
controlling circuit
signal controlling
microcomputer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12389279A
Other languages
Japanese (ja)
Inventor
Fumio Tsujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12389279A priority Critical patent/JPS5647827A/en
Publication of JPS5647827A publication Critical patent/JPS5647827A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE: To prevent a malfunction by closing a buffer provided between the transistor array and the peripheral control LSI, at the making time of power.
CONSTITUTION: At the making time of power, the peripheral control LSI11 is reset by the reset function, and at the same time the flip-flop (FF)15 is set. Resulting from the foregoing, the buffer 16 becomes a cutoff state, and a leak current does not flow into the transistor array 10. Accordingly, the external device connected to the array 10 is not turned on. A signal of the address bus 5 resets the FF15 through the decoder 6, the buffer conducts, and the external device is controlled by a data.
COPYRIGHT: (C)1981,JPO&Japio
JP12389279A 1979-09-28 1979-09-28 Output signal controlling circuit of microcomputer system Pending JPS5647827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12389279A JPS5647827A (en) 1979-09-28 1979-09-28 Output signal controlling circuit of microcomputer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12389279A JPS5647827A (en) 1979-09-28 1979-09-28 Output signal controlling circuit of microcomputer system

Publications (1)

Publication Number Publication Date
JPS5647827A true JPS5647827A (en) 1981-04-30

Family

ID=14871922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12389279A Pending JPS5647827A (en) 1979-09-28 1979-09-28 Output signal controlling circuit of microcomputer system

Country Status (1)

Country Link
JP (1) JPS5647827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617137A (en) * 1984-06-19 1986-01-13 Sanko Kuki Sochi Kk Operating method of differential pressure intercepting transfer device for pulverulent granule

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617137A (en) * 1984-06-19 1986-01-13 Sanko Kuki Sochi Kk Operating method of differential pressure intercepting transfer device for pulverulent granule
JPH0127933B2 (en) * 1984-06-19 1989-05-31 Sanko Air Plant

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