JPS5642826A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5642826A
JPS5642826A JP11898679A JP11898679A JPS5642826A JP S5642826 A JPS5642826 A JP S5642826A JP 11898679 A JP11898679 A JP 11898679A JP 11898679 A JP11898679 A JP 11898679A JP S5642826 A JPS5642826 A JP S5642826A
Authority
JP
Japan
Prior art keywords
master
clock
signal lines
clock pulse
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11898679A
Other languages
Japanese (ja)
Inventor
Kunio Numakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11898679A priority Critical patent/JPS5642826A/en
Publication of JPS5642826A publication Critical patent/JPS5642826A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the number of the signal lines to be connected, by using both the clock and master signal lines for the two-way transmission line in the data processing system in which the timing mechanism included in each of several data processors posseses the synchronous timing function.
CONSTITUTION: The data processor includes the following units: the clock pulse generators 21a and 21b; the master/slave flip-flops 24a and 24b which supply the master signals to the master signal lines when the data processor functions as the master unit; the clock driving circuits 25a and 25b which supply the clock pulses to the clock signal lines when the master signal is supplied; and the timing mechanisms 28a and 28b which count the time by the clock pulse supplied from the clock signal line when the master signal is transmitted through the master signal line and then count the time by the clock pulse generated from the clock pulse generator in case no master signal is transmitted respectively. As a result, the number of the signal lines connected to the data processor can be decreased by the two-way transmission.
COPYRIGHT: (C)1981,JPO&Japio
JP11898679A 1979-09-17 1979-09-17 Data processing system Pending JPS5642826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11898679A JPS5642826A (en) 1979-09-17 1979-09-17 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11898679A JPS5642826A (en) 1979-09-17 1979-09-17 Data processing system

Publications (1)

Publication Number Publication Date
JPS5642826A true JPS5642826A (en) 1981-04-21

Family

ID=14750172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11898679A Pending JPS5642826A (en) 1979-09-17 1979-09-17 Data processing system

Country Status (1)

Country Link
JP (1) JPS5642826A (en)

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