JPS5633735B2 - - Google Patents
Info
- Publication number
- JPS5633735B2 JPS5633735B2 JP14772174A JP14772174A JPS5633735B2 JP S5633735 B2 JPS5633735 B2 JP S5633735B2 JP 14772174 A JP14772174 A JP 14772174A JP 14772174 A JP14772174 A JP 14772174A JP S5633735 B2 JPS5633735 B2 JP S5633735B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US438511A US3873820A (en) | 1974-01-31 | 1974-01-31 | Apparatus for checking partial products in iterative multiply operations |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50110243A JPS50110243A (en:Method) | 1975-08-30 |
| JPS5633735B2 true JPS5633735B2 (en:Method) | 1981-08-05 |
Family
ID=23740912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14772174A Expired JPS5633735B2 (en:Method) | 1974-01-31 | 1974-12-24 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US3873820A (en:Method) |
| JP (1) | JPS5633735B2 (en:Method) |
| DE (1) | DE2503152A1 (en:Method) |
| FR (1) | FR2260139B1 (en:Method) |
| GB (1) | GB1443307A (en:Method) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4041292A (en) * | 1975-12-22 | 1977-08-09 | Honeywell Information Systems Inc. | High speed binary multiplication system employing a plurality of multiple generator circuits |
| US4181969A (en) * | 1978-01-18 | 1980-01-01 | Westinghouse Electric Corp. | System for detecting and isolating static bit faults in a network of arithmetic units |
| US4594679A (en) * | 1983-07-21 | 1986-06-10 | International Business Machines Corporation | High speed hardware multiplier for fixed floating point operands |
| JPS60140428A (ja) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | 除算装置 |
| US4870607A (en) * | 1986-07-03 | 1989-09-26 | Nec Corporation | Error detection carried out by the use of unused modulo-m code |
| US4924467A (en) * | 1988-08-24 | 1990-05-08 | Unisys Corporation | System for checking duplicate logic using complementary residue codes to achieve high error coverage with a minimum of interface signals |
| US5081629A (en) * | 1989-05-08 | 1992-01-14 | Unisys Corporation | Fault isolation for multiphase clock signals supplied to dual modules which are checked by comparison using residue code generators |
| US5253195A (en) * | 1991-09-26 | 1993-10-12 | International Business Machines Corporation | High speed multiplier |
| WO2005124578A2 (en) * | 2004-06-16 | 2005-12-29 | Discretix Technologies Ltd | System, method and apparatus of error detection during a modular operation |
| US7769795B1 (en) * | 2005-06-03 | 2010-08-03 | Oracle America, Inc. | End-to-end residue-based protection of an execution pipeline that supports floating point operations |
| US8433742B2 (en) * | 2008-08-06 | 2013-04-30 | Oracle America, Inc. | Modulus-based error-checking technique |
| US8566383B2 (en) * | 2008-10-17 | 2013-10-22 | International Business Machines Corporation | Distributed residue-checking of a floating point unit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3098994A (en) * | 1956-10-26 | 1963-07-23 | Itt | Self checking digital computer system |
| US3659089A (en) * | 1970-12-23 | 1972-04-25 | Ibm | Error detecting and correcting system and method |
| US3814923A (en) * | 1973-01-02 | 1974-06-04 | Bell Telephone Labor Inc | Error detection system |
-
1974
- 1974-01-31 US US438511A patent/US3873820A/en not_active Expired - Lifetime
- 1974-12-05 FR FR7441669A patent/FR2260139B1/fr not_active Expired
- 1974-12-11 GB GB5365474A patent/GB1443307A/en not_active Expired
- 1974-12-24 JP JP14772174A patent/JPS5633735B2/ja not_active Expired
-
1975
- 1975-01-27 DE DE19752503152 patent/DE2503152A1/de active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2260139A1 (en:Method) | 1975-08-29 |
| GB1443307A (en) | 1976-07-21 |
| JPS50110243A (en:Method) | 1975-08-30 |
| DE2503152A1 (de) | 1975-08-07 |
| FR2260139B1 (en:Method) | 1977-05-20 |
| US3873820A (en) | 1975-03-25 |