JPS5632847A - Channel monitoring circuit - Google Patents
Channel monitoring circuitInfo
- Publication number
- JPS5632847A JPS5632847A JP10893379A JP10893379A JPS5632847A JP S5632847 A JPS5632847 A JP S5632847A JP 10893379 A JP10893379 A JP 10893379A JP 10893379 A JP10893379 A JP 10893379A JP S5632847 A JPS5632847 A JP S5632847A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- threshold level
- counter
- inputted
- certain time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Abstract
PURPOSE:To send out an alarm by judging that when a demodulated signal exceeds a predetermined threshold level continuously for more than a certain time, a channel becomes abnormal, by monitoring over whether the demodulated signal exceeds the threshold level continuously for more than the certain time by comparing the demodulated signal to the threshold level at a reception side. CONSTITUTION:Demodulated signal (a) is compared with positive threshold level +Vth and negative threshold level -Vth by voltage comparators 304 and 306 to generate logical outputs 305 and 307. Logical outputs 305 and 307 are inputted to NOR gate 308 to generate signal 309, which is inputted to counter 310 as a reset signal. To counter 310, clock signal 311 whose repetitive frequency is previously known is inputted and carry signal 312 is outputted when the counter is placed in the full-count state, but when reset signal 309 increases in level to ''H'' in process of counting, the counter is reset and restarts counting. Therefore, if the carry signal is outputted, the reset signal is not held at ''H'' for more than a certain time, which is considered to be abnormality.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10893379A JPS5632847A (en) | 1979-08-27 | 1979-08-27 | Channel monitoring circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10893379A JPS5632847A (en) | 1979-08-27 | 1979-08-27 | Channel monitoring circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5632847A true JPS5632847A (en) | 1981-04-02 |
Family
ID=14497328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10893379A Pending JPS5632847A (en) | 1979-08-27 | 1979-08-27 | Channel monitoring circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5632847A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0144839A2 (en) * | 1983-11-18 | 1985-06-19 | Nec Corporation | Squelch signal generator capable of generating a squelch signal with a high reliability |
-
1979
- 1979-08-27 JP JP10893379A patent/JPS5632847A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0144839A2 (en) * | 1983-11-18 | 1985-06-19 | Nec Corporation | Squelch signal generator capable of generating a squelch signal with a high reliability |
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