JPS5630348A - Frame transmitting-receiving method - Google Patents
Frame transmitting-receiving methodInfo
- Publication number
- JPS5630348A JPS5630348A JP10576479A JP10576479A JPS5630348A JP S5630348 A JPS5630348 A JP S5630348A JP 10576479 A JP10576479 A JP 10576479A JP 10576479 A JP10576479 A JP 10576479A JP S5630348 A JPS5630348 A JP S5630348A
- Authority
- JP
- Japan
- Prior art keywords
- bit string
- circuit
- continuous
- fixed length
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To make it possible to reduce the cost by using inexpensive elements when providing a circuit to every line by increasing an arithmetic speed by performing arithmetic of every bit string, unitized to a fixed length, simultaneously in frame transmission and reception. CONSTITUTION:When a bit string of a fixed length arranged in parallel on a transmission line arrives, continuous-[1]-pattern detecting circuit 1 finds the number of continuous [1]s from the head and tail of the bit string. On the basis of this number and that of continuous [1]s right before the arrival bit string stored in memory 3, pattern detecting circuit 4 detects various patterns and, on flag detection, sends out information F on the flag position of the arrival bit string. On aport, idle detection, pieces of information A and I are sent out. Zero-deleting circuit 5 detects [0] inserted for transmissivity and performs deletion. Then, parallel shifter 10 extracts a bit string of the fixed length newly and CRC arithmetic circuit 11 processes the constant-length bit string in parallel as it is.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54105764A JPS6013627B2 (en) | 1979-08-20 | 1979-08-20 | Frame transmission/reception method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54105764A JPS6013627B2 (en) | 1979-08-20 | 1979-08-20 | Frame transmission/reception method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5630348A true JPS5630348A (en) | 1981-03-26 |
JPS6013627B2 JPS6013627B2 (en) | 1985-04-08 |
Family
ID=14416253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54105764A Expired JPS6013627B2 (en) | 1979-08-20 | 1979-08-20 | Frame transmission/reception method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6013627B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61102848A (en) * | 1984-10-25 | 1986-05-21 | Nippon Telegr & Teleph Corp <Ntt> | Transmission data generating device |
JPH0234067A (en) * | 1988-06-16 | 1990-02-05 | Internatl Business Mach Corp <Ibm> | Parallel processing of bit stream |
JPH05252234A (en) * | 1991-11-29 | 1993-09-28 | Internatl Business Mach Corp <Ibm> | Parallel processing method in remote communication device including dsp for hdlc/sdlc bit-stream transmission and reception |
-
1979
- 1979-08-20 JP JP54105764A patent/JPS6013627B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61102848A (en) * | 1984-10-25 | 1986-05-21 | Nippon Telegr & Teleph Corp <Ntt> | Transmission data generating device |
JPH0234067A (en) * | 1988-06-16 | 1990-02-05 | Internatl Business Mach Corp <Ibm> | Parallel processing of bit stream |
JPH05252234A (en) * | 1991-11-29 | 1993-09-28 | Internatl Business Mach Corp <Ibm> | Parallel processing method in remote communication device including dsp for hdlc/sdlc bit-stream transmission and reception |
JPH07123261B2 (en) * | 1991-11-29 | 1995-12-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Parallel processing method in communication device |
Also Published As
Publication number | Publication date |
---|---|
JPS6013627B2 (en) | 1985-04-08 |
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