JPS5624827A - Operation check system for counter group - Google Patents

Operation check system for counter group

Info

Publication number
JPS5624827A
JPS5624827A JP10027679A JP10027679A JPS5624827A JP S5624827 A JPS5624827 A JP S5624827A JP 10027679 A JP10027679 A JP 10027679A JP 10027679 A JP10027679 A JP 10027679A JP S5624827 A JPS5624827 A JP S5624827A
Authority
JP
Japan
Prior art keywords
signal
identity
circuit
significant
counter group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10027679A
Other languages
Japanese (ja)
Inventor
Shinsuke Nomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10027679A priority Critical patent/JPS5624827A/en
Publication of JPS5624827A publication Critical patent/JPS5624827A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make it possible to detect securely an error of a counter group including a trigger system with a simple circuit constitution by finding an identity comparison signal as to the least significant digit bit of each counter and the least significant bit of an initialized value and its inverted signal, and then by operating AND between the both. CONSTITUTION:Exclusive-OR circuit 4, 5 and 6 detect identies between the least significant bits 20, 21 and 22 of counters 1, 2 and 3 that count up by one in every operation period and the least significant bits 10, 11 and 12 of their initial values 13, 14 and 15 to generate identity signals 23, 25 and 27 and inverted signals 24, 26 and 28 of them. AND circuit 9 operates AND between identity signal 30 and inverted signal 31 and in accordance with its output, the state of operation is decided.
JP10027679A 1979-08-08 1979-08-08 Operation check system for counter group Pending JPS5624827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10027679A JPS5624827A (en) 1979-08-08 1979-08-08 Operation check system for counter group

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10027679A JPS5624827A (en) 1979-08-08 1979-08-08 Operation check system for counter group

Publications (1)

Publication Number Publication Date
JPS5624827A true JPS5624827A (en) 1981-03-10

Family

ID=14269670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10027679A Pending JPS5624827A (en) 1979-08-08 1979-08-08 Operation check system for counter group

Country Status (1)

Country Link
JP (1) JPS5624827A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299410A (en) * 1987-05-28 1988-12-06 Nec Corp Frequency division circuit
JPH01257362A (en) * 1988-04-07 1989-10-13 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299410A (en) * 1987-05-28 1988-12-06 Nec Corp Frequency division circuit
JPH01257362A (en) * 1988-04-07 1989-10-13 Fujitsu Ltd Semiconductor device

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