JPS5624659A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5624659A
JPS5624659A JP10001979A JP10001979A JPS5624659A JP S5624659 A JPS5624659 A JP S5624659A JP 10001979 A JP10001979 A JP 10001979A JP 10001979 A JP10001979 A JP 10001979A JP S5624659 A JPS5624659 A JP S5624659A
Authority
JP
Japan
Prior art keywords
signal
mpig
irl
program
user program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10001979A
Other languages
Japanese (ja)
Inventor
Kazutoshi Michioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10001979A priority Critical patent/JPS5624659A/en
Publication of JPS5624659A publication Critical patent/JPS5624659A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE: To carry out the access protection and memory protection in a simple circuit by defining the signal IRL for inhibiting relocation in the address area of the micro instruction and the memory protection release signal MPIG.
CONSTITUTION: In the case of referring to a common data commonly using a plurality of programs from a certain one user program, the control is transferred to the supervisor SUP program once. Herein, by setting to SPU mode, FF4 is set and in the case where the signal IRL is 0, the signal MPIG is impressed to the main memory device 1 to make accessible to all the areas on the device 1. SUP program reads out the data from the device 1, and after transmitting to the user program, the control is returned to the user program. According to this, FF4 is reset, the signal MPIG is made invalid. In addition, when the signal IRL is 0, the relocation register 5 is selected.
COPYRIGHT: (C)1981,JPO&Japio
JP10001979A 1979-08-06 1979-08-06 Memory control system Pending JPS5624659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10001979A JPS5624659A (en) 1979-08-06 1979-08-06 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10001979A JPS5624659A (en) 1979-08-06 1979-08-06 Memory control system

Publications (1)

Publication Number Publication Date
JPS5624659A true JPS5624659A (en) 1981-03-09

Family

ID=14262834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10001979A Pending JPS5624659A (en) 1979-08-06 1979-08-06 Memory control system

Country Status (1)

Country Link
JP (1) JPS5624659A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229161A (en) * 1984-04-27 1985-11-14 Hitachi Ltd Locking system of main storage
JPS61221835A (en) * 1985-03-12 1986-10-02 Fujitsu Ltd Controlling system for memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229161A (en) * 1984-04-27 1985-11-14 Hitachi Ltd Locking system of main storage
JPS61221835A (en) * 1985-03-12 1986-10-02 Fujitsu Ltd Controlling system for memory device
JPH0157374B2 (en) * 1985-03-12 1989-12-05 Fujitsu Ltd

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