JPS5623056A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS5623056A JPS5623056A JP9896279A JP9896279A JPS5623056A JP S5623056 A JPS5623056 A JP S5623056A JP 9896279 A JP9896279 A JP 9896279A JP 9896279 A JP9896279 A JP 9896279A JP S5623056 A JPS5623056 A JP S5623056A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- response
- retrial
- response signal
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To prevent the system-down, by producing the failure information signal and making definite the time for retrial, if the retrial request is not released within the predetermined time even with repetitive retrials, through the addition of the response monitor circuit to the system. CONSTITUTION:With the request indication circuit 3 of the data transfer units 1, 2, the request signal 101 is fed to the common bus 100. This signal 101 is received with the transfer unit 1 or 2, and either one response signal out of the ACK response signal 102, NACK response signal 103 and WAIT response signal 104 is fed from the respective response circuit 4 to the common bus 100. Further, the transfer units 1, 2 operate the response monitor circuit 5 when the request signal 101 is transmitted to start the monitor of the response signal and the monitor is ended when the signals 102, 103 are received as response signal. Further, when the signal 104 is received, retrial is repetitively made and if the retrial is not released within predetermined time, failure information signal is produced to avoid the system-down.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9896279A JPS5623056A (en) | 1979-08-02 | 1979-08-02 | Data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9896279A JPS5623056A (en) | 1979-08-02 | 1979-08-02 | Data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5623056A true JPS5623056A (en) | 1981-03-04 |
Family
ID=14233688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9896279A Pending JPS5623056A (en) | 1979-08-02 | 1979-08-02 | Data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5623056A (en) |
-
1979
- 1979-08-02 JP JP9896279A patent/JPS5623056A/en active Pending
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