JPS5616337A - Monitor system for delay amount of transmission line - Google Patents
Monitor system for delay amount of transmission lineInfo
- Publication number
- JPS5616337A JPS5616337A JP9208779A JP9208779A JPS5616337A JP S5616337 A JPS5616337 A JP S5616337A JP 9208779 A JP9208779 A JP 9208779A JP 9208779 A JP9208779 A JP 9208779A JP S5616337 A JPS5616337 A JP S5616337A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transmission line
- pulse
- delay amount
- delay time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
- H04B3/462—Testing group delay or phase shift, e.g. timing jitter
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
PURPOSE:To secure an accurate monitor for the delay amount of the transmission line with a simple method, by transmitting the pilot pulse having a longer repetitive period than the folded propagation delay time of the transmission line and then measuring the delay time during which the pilot pulse is floded along the transmission line and then fed back. CONSTITUTION:The clock pulse sent from the main oscillating circuit is divided into 1/n through dividing circuit 12 to be turned into pilot pulse (g). The period of pulse (g) is set longer than the folded propagation delay time of the transmission line. The output of circuit 12 is supplied to frame pulse generating circuit 13 as well as pseudo signal generating circuit 14, and the outputs of circuits 13 and 14 are converted into bipolar signals (e) through OR circuit 15 and unipolar-bipolar converting circuit 16 to be delivered. Signal (f) which is folded along the transmission line and then fed back receives extraction of the clock signal via bipolar-unipolar converting circuit 20, frame pulse detecting circuit 21 and synchronizing circuit 22 each. This clock signal is then divided into 1/n through dividing circuit 23 to generate pilot pulse (h). Both pulses (g) and (h) are supplied to pulse interval measuring circuit 26 for measurement of the delay amount of the transmission line. Thus an accurate monitor is possible for the delay amount of the transmssion line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9208779A JPS5616337A (en) | 1979-07-19 | 1979-07-19 | Monitor system for delay amount of transmission line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9208779A JPS5616337A (en) | 1979-07-19 | 1979-07-19 | Monitor system for delay amount of transmission line |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5616337A true JPS5616337A (en) | 1981-02-17 |
Family
ID=14044651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9208779A Pending JPS5616337A (en) | 1979-07-19 | 1979-07-19 | Monitor system for delay amount of transmission line |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5616337A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58214U (en) * | 1981-06-25 | 1983-01-05 | 三菱電機株式会社 | air conditioner |
JPS62163694U (en) * | 1986-04-07 | 1987-10-17 |
-
1979
- 1979-07-19 JP JP9208779A patent/JPS5616337A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58214U (en) * | 1981-06-25 | 1983-01-05 | 三菱電機株式会社 | air conditioner |
JPS6212170Y2 (en) * | 1981-06-25 | 1987-03-27 | ||
JPS62163694U (en) * | 1986-04-07 | 1987-10-17 |
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