JPS56162546A - Automatic display switching device - Google Patents
Automatic display switching deviceInfo
- Publication number
- JPS56162546A JPS56162546A JP6854181A JP6854181A JPS56162546A JP S56162546 A JPS56162546 A JP S56162546A JP 6854181 A JP6854181 A JP 6854181A JP 6854181 A JP6854181 A JP 6854181A JP S56162546 A JPS56162546 A JP S56162546A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- display
- time
- frequency
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/02—Indicating arrangements
- H03J1/04—Indicating arrangements with optical indicating means
- H03J1/045—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like
- H03J1/047—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like using electronic means, e.g. LED's
- H03J1/048—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like using electronic means, e.g. LED's with digital indication
Abstract
PURPOSE:To display a frequency and time with excellent operability by displaying the frequency in auto or manual channel selection exclusively and the time normally by one display device. CONSTITUTION:A gate TG2 is opened normally by the output of an FF18 and the output of a clocking part 13 is applied to a decoder 11 to perform the digital display of the time. When a keyboard 15 is operated for manual or autotuning, a gate circuit 17 turns on to set the FF18 and then while the gate TG2 is closed, a gate TG1 is opened. Therefore, the output of a digital tuner part 12 is applied to the decoder 11 to perform the display of a reception frequency on display devices D1-D4. In tuning, a pulse is sent from the tuner part 12 to reset the FF18 and then while the gate TG1 is closed, the gate TG2 is opened to send the signal of the clocking part 13 to the decoder 11 for time display. Thus, the frequency and time are displayed with excellent operability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6854181A JPS5920292B2 (en) | 1981-05-07 | 1981-05-07 | clock digital tuner |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6854181A JPS5920292B2 (en) | 1981-05-07 | 1981-05-07 | clock digital tuner |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56162546A true JPS56162546A (en) | 1981-12-14 |
JPS5920292B2 JPS5920292B2 (en) | 1984-05-12 |
Family
ID=13376703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6854181A Expired JPS5920292B2 (en) | 1981-05-07 | 1981-05-07 | clock digital tuner |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5920292B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6072044U (en) * | 1983-10-20 | 1985-05-21 | 三洋電機株式会社 | receiver with clock |
-
1981
- 1981-05-07 JP JP6854181A patent/JPS5920292B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6072044U (en) * | 1983-10-20 | 1985-05-21 | 三洋電機株式会社 | receiver with clock |
JPH0215416Y2 (en) * | 1983-10-20 | 1990-04-25 |
Also Published As
Publication number | Publication date |
---|---|
JPS5920292B2 (en) | 1984-05-12 |
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