JPS56153401A - Setter - Google Patents
SetterInfo
- Publication number
- JPS56153401A JPS56153401A JP5628080A JP5628080A JPS56153401A JP S56153401 A JPS56153401 A JP S56153401A JP 5628080 A JP5628080 A JP 5628080A JP 5628080 A JP5628080 A JP 5628080A JP S56153401 A JPS56153401 A JP S56153401A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- computer
- counter
- plant
- over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B7/00—Arrangements for obtaining smooth engagement or disengagement of automatic control
- G05B7/02—Arrangements for obtaining smooth engagement or disengagement of automatic control electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Control By Computers (AREA)
- Feedback Control In General (AREA)
Abstract
PURPOSE:To perform bumpless changing-over of fast response speeds with high accuracy by providing a counter which makes counting in accordance with the analog signals from a backup device or the like and sets the output of a computer to a control system which incorporates the computer in a plant or the like. CONSTITUTION:A setter 6 constitutes an interface of a computer 2, an analong control device 3, a manual operating machine 4, and a plant 5, and is set in accordance with the control mode selection signal (f). First, in the manual mode, the signal (g) from the operating device 4 is inputted by the signal (f) to a calculator 64 via a signal change-over device 62. This counter 64 makes up or down counting of the reference clock signal (j) of an oscillator 63. The count output thereof is D/A converted 65, and the signal (m) is outputted to the plant 5. In the automatic mode, the analog signal (n) of the device 3 is counted 64 via a comparator 61. In the computer mode, the digital signal (k) of the computer 2 is set as it is in the counter 64. Further, the count output is fed back as signals (l), (m), whereby the bumpless changing-over is accomplished.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5628080A JPS56153401A (en) | 1980-04-30 | 1980-04-30 | Setter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5628080A JPS56153401A (en) | 1980-04-30 | 1980-04-30 | Setter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56153401A true JPS56153401A (en) | 1981-11-27 |
Family
ID=13022674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5628080A Pending JPS56153401A (en) | 1980-04-30 | 1980-04-30 | Setter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56153401A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60195601A (en) * | 1984-03-16 | 1985-10-04 | Toshiba Eng Co Ltd | Setter |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4946081A (en) * | 1972-09-11 | 1974-05-02 | ||
JPS5012074A (en) * | 1972-06-26 | 1975-02-07 |
-
1980
- 1980-04-30 JP JP5628080A patent/JPS56153401A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5012074A (en) * | 1972-06-26 | 1975-02-07 | ||
JPS4946081A (en) * | 1972-09-11 | 1974-05-02 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60195601A (en) * | 1984-03-16 | 1985-10-04 | Toshiba Eng Co Ltd | Setter |
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