JPS56152394A - Channel test system for time division system digital exchange - Google Patents

Channel test system for time division system digital exchange

Info

Publication number
JPS56152394A
JPS56152394A JP5542580A JP5542580A JPS56152394A JP S56152394 A JPS56152394 A JP S56152394A JP 5542580 A JP5542580 A JP 5542580A JP 5542580 A JP5542580 A JP 5542580A JP S56152394 A JPS56152394 A JP S56152394A
Authority
JP
Japan
Prior art keywords
channel
memory
information
idle
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5542580A
Other languages
Japanese (ja)
Inventor
Kosei Hori
Takashi Okuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5542580A priority Critical patent/JPS56152394A/en
Publication of JPS56152394A publication Critical patent/JPS56152394A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To obtain a simple channel test system, by setting test information to a channel holding memory and by using one idle channel to test the channel. CONSTITUTION:Sending test information STD is written into address Hi of channel holding memory HM by central control device CC. Idle information of channel (i) is stored in bit ID of memory HM. Selecting circuit SEL transmits the signal from voice memory SPM to coding and decoding circuit CODEC if the channel is busy in the assigned time slot; and if the channel is idle, circuit SEL transmits the signal of memory HM to circuit CODEC. Circuit CODEC returns information STD, and returned information RTD is written in memory SPM. Device CC compares information STD on memory HM and information RTD on memory SPM with each other to discriminate whether the channel is correct or not.
JP5542580A 1980-04-28 1980-04-28 Channel test system for time division system digital exchange Pending JPS56152394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5542580A JPS56152394A (en) 1980-04-28 1980-04-28 Channel test system for time division system digital exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5542580A JPS56152394A (en) 1980-04-28 1980-04-28 Channel test system for time division system digital exchange

Publications (1)

Publication Number Publication Date
JPS56152394A true JPS56152394A (en) 1981-11-25

Family

ID=12998218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5542580A Pending JPS56152394A (en) 1980-04-28 1980-04-28 Channel test system for time division system digital exchange

Country Status (1)

Country Link
JP (1) JPS56152394A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171803A2 (en) * 1984-08-15 1986-02-19 Fujitsu Limited Time division exchange for carrying out a loop-back test

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171803A2 (en) * 1984-08-15 1986-02-19 Fujitsu Limited Time division exchange for carrying out a loop-back test

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