JPS56152303A - Detecting circuit for high gain - Google Patents

Detecting circuit for high gain

Info

Publication number
JPS56152303A
JPS56152303A JP5539780A JP5539780A JPS56152303A JP S56152303 A JPS56152303 A JP S56152303A JP 5539780 A JP5539780 A JP 5539780A JP 5539780 A JP5539780 A JP 5539780A JP S56152303 A JPS56152303 A JP S56152303A
Authority
JP
Japan
Prior art keywords
voltage
emitter
transistor
bias voltage
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5539780A
Other languages
Japanese (ja)
Inventor
Mitsunori Tsuchiya
Tetsuo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP5539780A priority Critical patent/JPS56152303A/en
Publication of JPS56152303A publication Critical patent/JPS56152303A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/14—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles
    • H03D1/18—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles of semiconductor devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)

Abstract

PURPOSE:To prevent generation of the offset voltage, by providing a detecting transistor by which a prescribed bias voltage is applied to an emitter and a buffer transistor in the output of the amplifying circuit to amplify and detect the input signal. CONSTITUTION:Since the feedback circuit of amplifying circuit 2 feeds back 100% DC, the emitter voltage of buffer transistor TRQ1 becomes equal to DC bias voltage V1. The emitter voltage of TRQ4 is higher than bias voltage V1 by voltage drop components due to constant current I0 and resistance R9 because voltages between bases and emitters of TRs Q9 and Q10 are equal to each other. Consequently, detecting transistor Q4 is biased at the class ''C'' operation point, and no bias current for no signal is flowed.
JP5539780A 1980-04-28 1980-04-28 Detecting circuit for high gain Pending JPS56152303A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5539780A JPS56152303A (en) 1980-04-28 1980-04-28 Detecting circuit for high gain

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5539780A JPS56152303A (en) 1980-04-28 1980-04-28 Detecting circuit for high gain

Publications (1)

Publication Number Publication Date
JPS56152303A true JPS56152303A (en) 1981-11-25

Family

ID=12997387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5539780A Pending JPS56152303A (en) 1980-04-28 1980-04-28 Detecting circuit for high gain

Country Status (1)

Country Link
JP (1) JPS56152303A (en)

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