JPS56147252A - Address control circuit - Google Patents

Address control circuit

Info

Publication number
JPS56147252A
JPS56147252A JP5113880A JP5113880A JPS56147252A JP S56147252 A JPS56147252 A JP S56147252A JP 5113880 A JP5113880 A JP 5113880A JP 5113880 A JP5113880 A JP 5113880A JP S56147252 A JPS56147252 A JP S56147252A
Authority
JP
Japan
Prior art keywords
counter
address
clock pulses
designated
designates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5113880A
Other languages
Japanese (ja)
Inventor
Makoto Inagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5113880A priority Critical patent/JPS56147252A/en
Publication of JPS56147252A publication Critical patent/JPS56147252A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To designate an address without using a high frequency, by setting constants as addresses to be designated to respective counters and by counting clock pulses from designated constants. CONSTITUTION:Clock pulse generating part 1 generates clock pulses and sends them to frequency dividing circuit 4, counters 9 and 11, and the gate circuit. Circuit 4 divides clock pulses and sends the frequency division output to counter 5. Counter 5 is provided with counter 12 which designates upper bits out of the count output and counter 11 which designates lower bits. Two constants corresponding to the address to be designated and the number to be jumped are set to counters 11 and 12, and clock pulses are counted, and counter 12 designates the upper address from the set numeric value, and counter 11 counts the set numeric value to designate the address of lower bits.
JP5113880A 1980-04-16 1980-04-16 Address control circuit Pending JPS56147252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5113880A JPS56147252A (en) 1980-04-16 1980-04-16 Address control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5113880A JPS56147252A (en) 1980-04-16 1980-04-16 Address control circuit

Publications (1)

Publication Number Publication Date
JPS56147252A true JPS56147252A (en) 1981-11-16

Family

ID=12878452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5113880A Pending JPS56147252A (en) 1980-04-16 1980-04-16 Address control circuit

Country Status (1)

Country Link
JP (1) JPS56147252A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919290A (en) * 1982-07-21 1984-01-31 スペリ・コ−ポレ−シヨン Common memory system
JPS62232799A (en) * 1986-04-02 1987-10-13 Nec Corp One chip microcomputer with built-in eprom

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919290A (en) * 1982-07-21 1984-01-31 スペリ・コ−ポレ−シヨン Common memory system
JPS62232799A (en) * 1986-04-02 1987-10-13 Nec Corp One chip microcomputer with built-in eprom

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