JPS56146337A - Monitor device for circuit quality - Google Patents
Monitor device for circuit qualityInfo
- Publication number
- JPS56146337A JPS56146337A JP4981680A JP4981680A JPS56146337A JP S56146337 A JPS56146337 A JP S56146337A JP 4981680 A JP4981680 A JP 4981680A JP 4981680 A JP4981680 A JP 4981680A JP S56146337 A JPS56146337 A JP S56146337A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- sine wave
- noise
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
PURPOSE:To ensure a high-accuracy monitor for the quality of circuit through a simple circuit constitution and even with just one circuit to be monitored, by securing an application of the sine wave received a distortion by the circuit noise as a noise level signal. CONSTITUTION:The sine wave signal (a) supplied from the sine wave oscillator 2 receives a distortion by the noise of communication circuit and is supplied to the shaping circuit 7. The circuit 7 generates the waveform shaping signal (h) and supplies it to the exclusive OR circuit 8. On the other hand, the rectangular wave oscillator 11 generates the reference waveform signal (i) having the same frequency as the oscillator 2. The reference sampling signal K synchronising with the signal (i) is converted into the sampling signal (l) according to an optional code transmitting speed through a multiplying circuit 12. A comparison is carried out at the exclusive OR circuit 8 between the signals (h) and (i), and a collation is given with the comparison result signal (j) by the signal (l) and at the AND circuit 9 to detect the element error (m). The error (m) is counted by the preset counting circuit 10, and the reference reduction signal (o) is delivered when the counting of the circuit 10 exceeds a certain reference value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4981680A JPS56146337A (en) | 1980-04-16 | 1980-04-16 | Monitor device for circuit quality |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4981680A JPS56146337A (en) | 1980-04-16 | 1980-04-16 | Monitor device for circuit quality |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56146337A true JPS56146337A (en) | 1981-11-13 |
JPS6313577B2 JPS6313577B2 (en) | 1988-03-26 |
Family
ID=12841635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4981680A Granted JPS56146337A (en) | 1980-04-16 | 1980-04-16 | Monitor device for circuit quality |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56146337A (en) |
-
1980
- 1980-04-16 JP JP4981680A patent/JPS56146337A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6313577B2 (en) | 1988-03-26 |
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