JPS56141618A - Digital-to-analog connecting circuit - Google Patents

Digital-to-analog connecting circuit

Info

Publication number
JPS56141618A
JPS56141618A JP4464480A JP4464480A JPS56141618A JP S56141618 A JPS56141618 A JP S56141618A JP 4464480 A JP4464480 A JP 4464480A JP 4464480 A JP4464480 A JP 4464480A JP S56141618 A JPS56141618 A JP S56141618A
Authority
JP
Japan
Prior art keywords
level
digital
output
output signal
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4464480A
Other languages
Japanese (ja)
Inventor
Seiji Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4464480A priority Critical patent/JPS56141618A/en
Publication of JPS56141618A publication Critical patent/JPS56141618A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To constitute this circuit so that a transient response is not generated in the interface with the analog circuit, by taking out a digital output from the tri-state gate, and always clamping its output terminal to an intermediate level. CONSTITUTION:The output terminal of the digital tri-state gate 4 is clamped to half voltage of the supply voltage VDD in advance. Accordingly, in case when there is no input signal A in the terminal A, the output signal E is VDD/2, if the input signal A is in an ''L'' level, the output signal E becomes an ''L'' level, and if the input signal A is in an ''H'' level, the output signal E becomes an ''H'' level. When this output signal E is taken out to the analog amplifier 2 through the capacitor 3, a transient phenomenon is generated, and it can be prevented that the zero potential is shifted.
JP4464480A 1980-04-07 1980-04-07 Digital-to-analog connecting circuit Pending JPS56141618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4464480A JPS56141618A (en) 1980-04-07 1980-04-07 Digital-to-analog connecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4464480A JPS56141618A (en) 1980-04-07 1980-04-07 Digital-to-analog connecting circuit

Publications (1)

Publication Number Publication Date
JPS56141618A true JPS56141618A (en) 1981-11-05

Family

ID=12697142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4464480A Pending JPS56141618A (en) 1980-04-07 1980-04-07 Digital-to-analog connecting circuit

Country Status (1)

Country Link
JP (1) JPS56141618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633633U (en) * 1986-06-21 1988-01-11

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633633U (en) * 1986-06-21 1988-01-11

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