JPS56140597A - Level shifting circuit and its driving method - Google Patents

Level shifting circuit and its driving method

Info

Publication number
JPS56140597A
JPS56140597A JP4430880A JP4430880A JPS56140597A JP S56140597 A JPS56140597 A JP S56140597A JP 4430880 A JP4430880 A JP 4430880A JP 4430880 A JP4430880 A JP 4430880A JP S56140597 A JPS56140597 A JP S56140597A
Authority
JP
Japan
Prior art keywords
switches
terminals
operational amplifier
side input
inversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4430880A
Other languages
Japanese (ja)
Other versions
JPS6236315B2 (en
Inventor
Tsutomu Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4430880A priority Critical patent/JPS56140597A/en
Publication of JPS56140597A publication Critical patent/JPS56140597A/en
Publication of JPS6236315B2 publication Critical patent/JPS6236315B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier

Landscapes

  • Amplifiers (AREA)
  • Networks Using Active Elements (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To set the extent of a shift in DC level independently of the gain of a signal component and without using a special constant voltage source, by providing an operational amplifier, capacitors and MOST switches. CONSTITUTION:Output terminal 40 os operational amplifier 30 is led to inversion- side input terminal 41 via capacitor 31 to form a negative feedback loop. In this negative feedback loop, MOST switch 34 is provided. Inversion-side input terminal 41, on the other hand, is led to terminals 42 and 43 of capacitors 32 and 33 connected to a point of zero volt at one-side terminals via MOST switches 37 and 38, and further terminals 42 and 43 are coupled with signal source 35 and voltage source 46 via MOST switches 35 and 36 respectively. Noninversion-side input teminal 39 of operational amplifier 30 is connected to the point of zero volt. Meanwhile, MOST switches 34-38 turn on-off repeatedly and periodically with control pulse voltages applied between terminals 47 and 48.
JP4430880A 1980-04-04 1980-04-04 Level shifting circuit and its driving method Granted JPS56140597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4430880A JPS56140597A (en) 1980-04-04 1980-04-04 Level shifting circuit and its driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4430880A JPS56140597A (en) 1980-04-04 1980-04-04 Level shifting circuit and its driving method

Publications (2)

Publication Number Publication Date
JPS56140597A true JPS56140597A (en) 1981-11-02
JPS6236315B2 JPS6236315B2 (en) 1987-08-06

Family

ID=12687856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4430880A Granted JPS56140597A (en) 1980-04-04 1980-04-04 Level shifting circuit and its driving method

Country Status (1)

Country Link
JP (1) JPS56140597A (en)

Also Published As

Publication number Publication date
JPS6236315B2 (en) 1987-08-06

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