JPS56138337A - Frequency converter and phase locked loop circuit - Google Patents

Frequency converter and phase locked loop circuit

Info

Publication number
JPS56138337A
JPS56138337A JP2500481A JP2500481A JPS56138337A JP S56138337 A JPS56138337 A JP S56138337A JP 2500481 A JP2500481 A JP 2500481A JP 2500481 A JP2500481 A JP 2500481A JP S56138337 A JPS56138337 A JP S56138337A
Authority
JP
Japan
Prior art keywords
frequency converter
locked loop
phase locked
loop circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2500481A
Other languages
Japanese (ja)
Inventor
Jiyubin Rein Rourensu
Buougun Raasen Einaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JPS56138337A publication Critical patent/JPS56138337A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/16Networks for phase shifting
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/06Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into an amplitude of current or voltage

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Supply And Distribution Of Alternating Current (AREA)
JP2500481A 1980-02-28 1981-02-24 Frequency converter and phase locked loop circuit Pending JPS56138337A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12534680A 1980-02-28 1980-02-28

Publications (1)

Publication Number Publication Date
JPS56138337A true JPS56138337A (en) 1981-10-28

Family

ID=22419316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2500481A Pending JPS56138337A (en) 1980-02-28 1981-02-24 Frequency converter and phase locked loop circuit

Country Status (4)

Country Link
JP (1) JPS56138337A (en)
DE (1) DE3106078A1 (en)
ES (1) ES8306299A1 (en)
IT (1) IT1135605B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854834A (en) * 1981-09-10 1983-03-31 ウエスチングハウス・エレクトリツク・コ−ポレ−シヨン Stationary reactive power compensating and netowrk stabilizing device
JPH04211519A (en) * 1991-02-12 1992-08-03 Seiko Epson Corp Voltage control oscillation circuit
US5513301A (en) * 1993-11-22 1996-04-30 Nec Corporation Image compression and decompression apparatus with reduced frame memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854834A (en) * 1981-09-10 1983-03-31 ウエスチングハウス・エレクトリツク・コ−ポレ−シヨン Stationary reactive power compensating and netowrk stabilizing device
JPH04211519A (en) * 1991-02-12 1992-08-03 Seiko Epson Corp Voltage control oscillation circuit
US5513301A (en) * 1993-11-22 1996-04-30 Nec Corporation Image compression and decompression apparatus with reduced frame memory

Also Published As

Publication number Publication date
ES499561A0 (en) 1982-09-01
DE3106078A1 (en) 1981-12-10
IT1135605B (en) 1986-08-27
ES8306299A1 (en) 1982-09-01
IT8119943A0 (en) 1981-02-24

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