JPH04211519A - Voltage control oscillation circuit - Google Patents
Voltage control oscillation circuitInfo
- Publication number
- JPH04211519A JPH04211519A JP3018748A JP1874891A JPH04211519A JP H04211519 A JPH04211519 A JP H04211519A JP 3018748 A JP3018748 A JP 3018748A JP 1874891 A JP1874891 A JP 1874891A JP H04211519 A JPH04211519 A JP H04211519A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- oscillation circuit
- frequency
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 83
- 230000002194 synthesizing effect Effects 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- 238000003786 synthesis reaction Methods 0.000 claims description 21
- 239000000470 constituent Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は位相固定ループ(PLL
,Phase Locked Loop)等に用いられ
る電圧制御発振回路に関する。本発明は電圧制御発振回
路の特にフリーラン周波数の安定化を計った回路に関す
る。[Industrial Application Field] The present invention relates to a phase-locked loop (PLL).
, Phase Locked Loop), etc. The present invention relates to a voltage controlled oscillation circuit, particularly to a circuit designed to stabilize the free run frequency.
【0002】0002
【従来の技術】従来より電圧制御発振回路は非常に多く
発表されている。図3に例としてPLL用1チップ相補
MOS集積回路(CMOS・IC)に用いられている電
圧制御発振回路を掲げる。NチャネルトランジスタN1
のゲートに加えられる制御電圧によりコンデンサC1に
流入する電流を制御し発振周波数をコントロールする。
抵抗R1,R2はそれぞれ制御電圧感度係数、フリーラ
ン周波数を決定する。2. Description of the Related Art A large number of voltage controlled oscillation circuits have been published in the past. FIG. 3 shows, as an example, a voltage controlled oscillation circuit used in a one-chip complementary MOS integrated circuit (CMOS-IC) for PLL. N-channel transistor N1
The current flowing into the capacitor C1 is controlled by the control voltage applied to the gate of the capacitor C1, thereby controlling the oscillation frequency. Resistors R1 and R2 determine the control voltage sensitivity coefficient and free run frequency, respectively.
【0003】また他の例として図4には特公昭56−8
6509により公知の電圧制御発振回路を示す。該回路
はリングオシレータに流入する電流をソースに接続され
たトランジスタT41〜T46のゲート電圧により制御
し発振周波数を制御するものである。この回路は図4の
回路に比較し外付部品が不要で消費電力、実装スペース
も小さい利点があるが正確で安定な発振回路は作りにく
い。
また図3の回路でも安定度は充分とは言えない。[0003] As another example, FIG.
6509 indicates a known voltage controlled oscillation circuit. This circuit controls the current flowing into the ring oscillator by the gate voltages of the transistors T41 to T46 connected to the sources, thereby controlling the oscillation frequency. This circuit has the advantage of requiring no external components and requiring less power consumption and mounting space than the circuit shown in FIG. 4, but it is difficult to create an accurate and stable oscillation circuit. Further, even the circuit shown in FIG. 3 cannot be said to have sufficient stability.
【0004】0004
【発明が解決しようとする課題】一般に電圧制御発振回
路にし安定度の要求されるのはフリーラン周波数及び電
圧制御感度係数である。前者は電圧制御発振回路の制御
端子に加えられる電圧(制御電圧)が基準レベルにとき
の発振周波数である。基準レベルは通常制御可能な入力
電圧範囲の中央、例えばCMOS・ICでは電源電圧の
1/2に選ばれ、制御電圧をVC・基準レベルの電圧を
VSとしてΔVCを
ΔVC=VC−VS ……………(1)と定義すれば
フリーラン周波数はΔVC=0のときの発振周波数と言
い直しても良い。電圧制御感度係数KVはfO=fC+
KV・ΔV ………(2)として定義される。fCは
フリーラン周波数、fOは電圧制御発振回路の発振周波
数である。Generally speaking, stability is required for a voltage controlled oscillator circuit in terms of the free run frequency and the voltage control sensitivity coefficient. The former is the oscillation frequency when the voltage (control voltage) applied to the control terminal of the voltage controlled oscillation circuit is at the reference level. The reference level is usually selected at the center of the controllable input voltage range, for example, 1/2 of the power supply voltage in CMOS/IC.If the control voltage is VC and the reference level voltage is VS, ΔVC is ΔVC=VC-VS... ...If defined as (1), the free-run frequency can be rephrased as the oscillation frequency when ΔVC=0. Voltage control sensitivity coefficient KV is fO=fC+
KV・ΔV (2) Defined as: fC is a free run frequency, and fO is an oscillation frequency of the voltage controlled oscillation circuit.
【0005】フリーラン周波数fCのドリフトはPLL
においては系のキャプチャレンジのドリフトとなって悪
影響があらわれる。また、回路部品定数のばらつきによ
るfCのばらつきは無視できない程度に大きく、従来は
コスト高を覚悟した上で高制度部品を用いるか、組立後
に半固定抵抗や半固定コンデンサにより調整、合せ込み
をする必要があった。また電圧制御感度係数KVのドリ
フトはPLLを構成した場合、系の応答速度のドリフト
となって悪影響があらわれる。[0005] The drift of the free run frequency fC is the PLL
In this case, the capture range of the system will drift, causing an adverse effect. In addition, the variation in fC due to variations in circuit component constants is too large to be ignored. Conventionally, high-precision components are used at the expense of high costs, or adjustments and matching are made using semi-fixed resistors or semi-fixed capacitors after assembly. There was a need. Further, when a PLL is configured, a drift in the voltage control sensitivity coefficient KV results in a drift in the response speed of the system, resulting in an adverse effect.
【0006】これ等のドリフトの原因は周囲温度の変化
、使用電源の変動、部品定数の経時変化等である。特に
fCの変動はこれ等の要因により大きくドリフトする。
一方KVは回路の構成部品の相対精度により決まる様に
することができ半導体集積回路技術等により素子値の絶
対精度はなくとも相対的に充分なトラッキング特性を持
たせることによりその変動を小さくできる。The causes of these drifts include changes in ambient temperature, fluctuations in the power supply used, and changes in component constants over time. In particular, the fluctuation of fC greatly drifts due to these factors. On the other hand, KV can be determined by the relative accuracy of the circuit components, and its fluctuation can be reduced by providing relatively sufficient tracking characteristics using semiconductor integrated circuit technology, etc., even if the element values do not have absolute accuracy.
【0007】本発明は従来の電圧制御発振回路のドリフ
トを押える回路方式に関するものであって回路の構成部
品の定数のばらつき変動による発振回路の定数(fC,
KV)の変動を小さくし回路の安定性を増大することに
ある。The present invention relates to a circuit system for suppressing the drift of a conventional voltage controlled oscillator circuit, and the oscillation circuit constant (fC,
The purpose of this invention is to reduce fluctuations in KV) and increase the stability of the circuit.
【0008】本発明の他の目的は回路定数の絶対精度に
対しての変動を抑えることにより集積回路化しやすい電
圧制御発振回路を提供することにある。Another object of the present invention is to provide a voltage controlled oscillator circuit that can be easily integrated into an integrated circuit by suppressing fluctuations in absolute accuracy of circuit constants.
【0009】[0009]
【課題を解決するための手段】本発明は、少なくとも以
下の構成要件
a.第1,第2の端子(109,110)に与えられた
信号を受けてそれ等の信号を合成し出力する第1の手段
−101
b.前記手段101と同じ特性を有する第2の手段−1
03
c.前記第1の信号合成手段101の信号により発振周
波数を制御される第1の発振回路−102d.前記発振
回路102と同じ特性を持ち前記第2の信号合成手段1
03の信号により制御される第2の発振回路−104
e.基準となる周波数の信号を発する手段−107を有
し、前記第2の発振回路104の出力は前記基準となる
周波数の信号を発する手段107より発せられる信号と
位相を比較し、その結果により前記第2の発振回路10
4の出力周波数を調整すべく前記第2の信号合成手段1
03の第2の入力端子112に信号を加える。また前記
第2の信号合成手段103の第1の入力端子111には
基準レベルとなるレベル信号を与え前記第1の信号合成
手段101の第2の入力端子110には前記第2の信号
合成手段103の第2の入力端子112に印加される信
号を与える。さらに前記第1の信号合成手段101の第
1の入力端子109を制御端子、第一の発振回路102
の出力を出力とすることを特徴とする。[Means for Solving the Problems] The present invention has at least the following constituent features a. First means-101 for receiving signals applied to the first and second terminals (109, 110), synthesizing and outputting the signals; b. Second means-1 having the same characteristics as the means 101
03 c. a first oscillation circuit whose oscillation frequency is controlled by the signal of the first signal synthesis means 101-102d. The second signal synthesis means 1 has the same characteristics as the oscillation circuit 102.
Second oscillation circuit controlled by signal 03-104 e. The output of the second oscillation circuit 104 is compared in phase with the signal emitted from the reference frequency signal 107, and based on the result, the output of the second oscillation circuit 104 is Second oscillation circuit 10
the second signal synthesizing means 1 to adjust the output frequency of 4;
A signal is applied to the second input terminal 112 of 03. Further, a level signal serving as a reference level is supplied to the first input terminal 111 of the second signal synthesizing means 103, and the second input terminal 110 of the first signal synthesizing means 101 is connected to the second signal synthesizing means. 103 provides a signal to be applied to a second input terminal 112 of 103 . Further, the first input terminal 109 of the first signal synthesizing means 101 is used as a control terminal, and the first oscillation circuit 102
It is characterized in that the output is the output.
【0010】0010
【実施例】図1は本発明の概念を示す図である。101
,103は同一の特性を有する様に設計された信号合成
手段で例えば端子109に与えられる信号(以下、電圧
値として話をすすめる。電流値、電荷値等他の物理量で
も話は同じである。)をV11、端子110に加わる信
号電圧をV21、信号合成手段101の出力端子114
にあらわれる電圧をV01とすると
V01=f(V11,V21) …………(3)fは任
意関数
の様な特性を有する回路である。以下、簡単のためにV
01=aV11+bV21+c ……(4)とする
。(a,b,cは定数)
同様に端子111、端子112に加えられる電圧をそれ
ぞれV12,V22 とし信号合成手段103の出力端
子115の電圧をV02としたとき
V02=aV12+bV22+c ………(5)とする
。102,104は特性のそろった電圧制御発振回路で
あり出力信号の周波数F1,F2 はF1=KV V0
1+d …………………(6)F2=KV V02+d
…………………(7)とする(dは定数)。107は
位相比較回路で電圧制御発振回路104の出力と安定な
周波数の発振をする発振回路(例えば水晶発振回路)の
出力信号と位相比較をしその位相差に比較した量の信号
を出力する。105はローパスフィルタ(LPF)で位
相比較回路の出力から希望する信号成分のみをとり出す
ために通常入れられる。
LPF105の出力は第2の信号合成回路103の第2
の入力端子112に負帰還する。すなわち第2の電圧制
御発振回路104、位相比較回路106、LPF105
、信号合成手段103はPLLを構成し第2の電圧制御
発振回路の発振周波数は発振回路107の発振周波数f
refと等しくなる。電圧制御発振回路104の出力周
波数は位相比較回路106、LPF105の特性により
frefと位相まで完全に一致させることもできるし、
またfrefの突発的な変化に対しては追従しない様に
することもできる。発振回路107は通常、充分安定な
発振をする回路を用いるので系の応答を速くしても問題
はない。また電圧制御発振回路104の出力周波数とf
refは周波数のみ追従し、位相は誤差があってもよい
から回路の構成はかなり自由度がある。発振回路107
が不安定でジッタ等を有する時は系の設計によりその影
響を軽減できる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the concept of the present invention. 101
, 103 are signal synthesis means designed to have the same characteristics, and for example, a signal (hereinafter referred to as a voltage value) applied to a terminal 109. The same applies to other physical quantities such as a current value and a charge value. ) is V11, the signal voltage applied to the terminal 110 is V21, and the output terminal 114 of the signal synthesis means 101 is
Letting the voltage appearing at V01 be V01, V01=f(V11, V21) (3) f is a circuit having characteristics like an arbitrary function. Below is V for simplicity.
01=aV11+bV21+c...(4). (a, b, c are constants) Similarly, when the voltages applied to the terminals 111 and 112 are V12 and V22, respectively, and the voltage at the output terminal 115 of the signal synthesizing means 103 is V02, V02=aV12+bV22+c (5) shall be. 102 and 104 are voltage controlled oscillator circuits with uniform characteristics, and the output signal frequencies F1 and F2 are F1=KV V0
1+d …………………(6) F2=KV V02+d
.........(7) (d is a constant). A phase comparison circuit 107 compares the phases of the output of the voltage controlled oscillation circuit 104 with the output signal of an oscillation circuit (for example, a crystal oscillation circuit) that oscillates at a stable frequency, and outputs a signal of an amount compared to the phase difference. A low pass filter (LPF) 105 is normally inserted to extract only desired signal components from the output of the phase comparison circuit. The output of the LPF 105 is sent to the second signal synthesizer circuit 103.
Negative feedback is provided to the input terminal 112 of. That is, the second voltage controlled oscillation circuit 104, the phase comparison circuit 106, and the LPF 105
, the signal synthesis means 103 constitutes a PLL, and the oscillation frequency of the second voltage controlled oscillation circuit is the oscillation frequency f of the oscillation circuit 107.
It becomes equal to ref. The output frequency of the voltage controlled oscillation circuit 104 can be completely matched with fref even in phase due to the characteristics of the phase comparator circuit 106 and the LPF 105.
Further, it is also possible to avoid following sudden changes in fref. Since the oscillation circuit 107 is normally a circuit that generates sufficiently stable oscillation, there is no problem even if the response of the system is made faster. Also, the output frequency of the voltage controlled oscillation circuit 104 and f
Since ref follows only the frequency and there may be an error in the phase, the circuit configuration has a considerable degree of freedom. Oscillation circuit 107
If the signal is unstable and has jitter, etc., the effect can be reduced by system design.
【0011】さて、電源電圧の変動、温度特性、経時変
化等により電圧制御発振回路104のフリーラン周波数
が変動した場合を考えよう。このとき系は自動的に端子
112に加わる電圧を上げ下げして電圧制御発振回路1
04の発振周波数はfrefを保つ。また第2の信号合
成手段103の第1の制御端子111に任意の電圧値を
与えた場合もその電圧値にかかわらず第2の電圧制御発
振回路の発振周波数はfrefとなる様、端子112の
電圧は自動的に調整される。Now, let us consider a case where the free run frequency of the voltage controlled oscillation circuit 104 fluctuates due to fluctuations in power supply voltage, temperature characteristics, changes over time, and the like. At this time, the system automatically increases or decreases the voltage applied to the terminal 112 to
The oscillation frequency of 04 is maintained at fref. Further, even if an arbitrary voltage value is applied to the first control terminal 111 of the second signal synthesizing means 103, the oscillation frequency of the second voltage controlled oscillation circuit will be fref regardless of the voltage value. Voltage will be adjusted automatically.
【0012】従って、第2の信号合成回路の第1の入力
端子111に基準となる電圧VSを与えると第2の入力
端子112は自動的にレベル調整され電圧制御発振回路
104の発振周波数frefに等しくなる。図1に示す
様に第2の信号合成手段103の第2の入力端子112
の電圧を第1の信号合成手段101の第2の入力端子1
10にも与えると第1、第2の信号合成手段、電圧制御
発振回路はそれぞれ特性がそろっているので第1の電圧
制御発振回路102の発振周波数は第1の信号合成手段
101の第1の入力端子109に与えられる電圧がVS
のときfrefとなる。frefを希望するフリーラン
周波数fCに等しく設定しておけば端子109の電圧が
VSのとき電圧制御発振回路102の発振周波数はfC
となる。従って図1の回路全体を端子109を制御端子
、113を出力端子とする電圧制御発振回路とすればフ
リーラン周波数がfCの電圧制御回路を実現できたこと
になる。 回路内の2つの信号合成手段101,10
3、電圧制御発振回路102,104の特性は等しいと
仮定して議論をしてきたが、この仮定は極めて妥当なも
のである。特にモノシリック集積回路化した場合、各々
は数ミリ角のチップ上に高精度で対称性よく作り込むこ
とができる。各々の回路は同時に製造されるため経時変
化があったとしても同一の経過時間であり特性が各々で
異なってくることは少ない。また電源電圧や温度変化に
対しても同一の電源にて使用されるし、また、きわめて
近い場所に配置されているため双方に温度差を生じ特性
が異なってくることも少ない。集積回路の設計時に各々
の回路の対称性を充分配慮しておけば、各特性の変動は
互いにキャンセルしあってドリフトの少ない安定な電圧
制御発振回路を実現できる。Therefore, when the reference voltage VS is applied to the first input terminal 111 of the second signal synthesis circuit, the level of the second input terminal 112 is automatically adjusted to match the oscillation frequency fref of the voltage controlled oscillation circuit 104. be equal. As shown in FIG. 1, the second input terminal 112 of the second signal combining means 103
is applied to the second input terminal 1 of the first signal combining means 101.
10, since the first and second signal synthesis means and the voltage controlled oscillation circuit have the same characteristics, the oscillation frequency of the first voltage controlled oscillation circuit 102 is the same as that of the first signal synthesis means 101. The voltage applied to the input terminal 109 is VS
When , it becomes fref. If fref is set equal to the desired free run frequency fC, the oscillation frequency of the voltage controlled oscillation circuit 102 will be fC when the voltage at the terminal 109 is VS.
becomes. Therefore, if the entire circuit of FIG. 1 is made into a voltage controlled oscillator circuit with terminal 109 as a control terminal and terminal 113 as an output terminal, a voltage controlled circuit with a free run frequency of fC can be realized. Two signal synthesis means 101, 10 in the circuit
3. The discussion has been made on the assumption that the voltage controlled oscillation circuits 102 and 104 have the same characteristics, but this assumption is extremely valid. In particular, when fabricated into a monolithic integrated circuit, each can be fabricated with high precision and good symmetry on a chip several millimeters square. Since each circuit is manufactured at the same time, even if there is a change over time, the elapsed time is the same, and the characteristics are unlikely to differ from each other. In addition, the same power source is used in response to changes in power supply voltage and temperature, and since they are located very close to each other, it is unlikely that temperature differences will occur between the two and the characteristics will differ. If sufficient consideration is given to the symmetry of each circuit when designing an integrated circuit, variations in each characteristic will cancel each other out, making it possible to realize a stable voltage-controlled oscillator circuit with little drift.
【0013】図2は以上の本発明の考え方にもとづき半
導体集積回路により実現できる電圧制御発振回路の具体
例を示す図である。201は信号合成回路でトランジス
タT1及びT2のゲート電圧を変えることにより各々の
ドレイン電流を変える。T1,T2のドレイン電流は合
成(加算)されトランジスタT13に流れ込み電圧に変
換される。この電圧は第1の電圧制御発振回路の制御電
圧であり、MOSトランジスタで構成される電圧制御発
振回路202に入力される。この回路はトランジスタT
7,T10,T8,T11,……T9,T12により構
成される奇数段のインバータによりリングオシレータを
構成し、各々のトランジスタのソースさらにトランジス
タT4,T5,…T6,T15,T16,…T17を直
列に入れ、これ等のトランジスタのゲート電位を制御す
ることによりリングオシレータに電源より流入する電流
を制御し発振周波数を制御するものである。本発明の例
では端子212,214の電位が低くなる程T13のド
レイン電圧(電圧制御発振回路202の制御電圧)が上
昇し発振周波数が上がる。すなわち(4)式においてa
,bが負、(6)式においてKVが正の場合である。端
子212,214のレベルが高い時に高い周波数で発振
させたければ例えば201,202の回路のトランジス
タの極性をすべて逆(PチャネルトランジスタをNチャ
ネルに、NチャネルトランジスタをPチャネルに)にす
れば、a,bが負、KVが負となり達成できる。205
,206は出力を得るためのバッファ回路である。FIG. 2 is a diagram showing a specific example of a voltage controlled oscillation circuit that can be realized by a semiconductor integrated circuit based on the above idea of the present invention. 201 is a signal synthesis circuit that changes the drain current of each transistor by changing the gate voltage of the transistors T1 and T2. The drain currents of T1 and T2 are combined (added) and flow into the transistor T13, where it is converted into a voltage. This voltage is the control voltage of the first voltage controlled oscillation circuit, and is input to the voltage controlled oscillation circuit 202 composed of MOS transistors. This circuit is a transistor T
7, T10, T8, T11,...T9, T12 constitute a ring oscillator with an odd number of stages of inverters, and the source of each transistor and further transistors T4, T5,...T6, T15, T16,...T17 are connected in series. By controlling the gate potential of these transistors, the current flowing into the ring oscillator from the power supply is controlled, and the oscillation frequency is controlled. In the example of the present invention, the lower the potential of the terminals 212 and 214, the higher the drain voltage of T13 (the control voltage of the voltage controlled oscillation circuit 202) and the higher the oscillation frequency. That is, in equation (4), a
, b are negative, and KV is positive in equation (6). If you want to oscillate at a high frequency when the level of terminals 212 and 214 is high, for example, if you reverse the polarity of all the transistors in the circuits 201 and 202 (P channel transistor to N channel, N channel transistor to P channel), This can be achieved when a and b are negative and KV is negative. 205
, 206 is a buffer circuit for obtaining an output.
【0014】203,204はそれぞれ201,202
と同様の回路構成を持つ信号合成回路、電圧制御発振回
路である。内部構成は同じなので図では内部を省略して
ある。第2の電圧制御発振回路の出力はバッファ207
を通し位相比較回路208に入力される。211は水晶
発振回路でフリーラン周波数の基準となる周波数fre
f(=fC)を発振する発振回路である。通常はこの信
号は位相比較回路208に入力され第2の電圧制御発振
回路204の出力と位相比較されるとともに他の回路の
タイミングクロック、システムクロックなどと共用され
る。もし他の回路の要求するクロック信号等の周波数と
希望するfCが異なる場合はノード219または218
の一方か双方に分周回路や周波数変換回路を入れること
により水晶発振回路211の発振周波数の整数倍、整数
分の1、それ等の差、整数ぶんの整数等にfCを設定す
ることが可能である。文周回路や周波数変換回路はデジ
タル回路で構成でき半導体集積回路化に際して何ら障害
は生じない。217はローパスフィルタで位相比較回路
208の出力に含まれる高周波成分を除去する。出力は
第2の信号合成回路203の第2の入力端子215に帰
還される。第1の入力端子213にはfCを発振させた
い入力信号レベル(基準レベル)を与えるべく電源電圧
を分圧する抵抗R11,R12が接続されている。抵抗
は半導体集積回路内に正確なものは作りにくいが相対精
度は非常に高く作ることが可能である。この端子には例
えばツエナーダイオードによる基準電圧等のもっと正確
な電圧源を接続しても良い。第1及び第2の信号の信号
合成回路の第2の入力端子214,215にはローパス
フィルタ217内部の異なったところから信号をとり出
し接続しているが抵抗R4はPLL系の安定化のために
必要な抵抗であって図1の場合と本質的に異なるもので
はない。[0014] 203 and 204 are 201 and 202, respectively.
This is a signal synthesis circuit and a voltage controlled oscillator circuit with a circuit configuration similar to that of . Since the internal configuration is the same, the internal parts are omitted in the figure. The output of the second voltage controlled oscillation circuit is the buffer 207
The signal is input to the phase comparator circuit 208 through. 211 is a crystal oscillator circuit, and the frequency fre is the reference for the free run frequency.
This is an oscillation circuit that oscillates f (=fC). Normally, this signal is input to the phase comparator circuit 208, where it is phase-compared with the output of the second voltage-controlled oscillation circuit 204, and is also shared with the timing clock, system clock, etc. of other circuits. If the frequency of the clock signal etc. required by another circuit is different from the desired fC, the node 219 or 218
By inserting a frequency divider circuit or a frequency conversion circuit into one or both of them, it is possible to set fC to an integer multiple of the oscillation frequency of the crystal oscillation circuit 211, an integer fraction, the difference thereof, an integer of an integer, etc. It is. The frequency conversion circuit and the frequency conversion circuit can be constructed with digital circuits, and there will be no problem when fabricating them into semiconductor integrated circuits. A low-pass filter 217 removes high frequency components contained in the output of the phase comparison circuit 208. The output is fed back to the second input terminal 215 of the second signal synthesis circuit 203. Resistors R11 and R12 are connected to the first input terminal 213 for dividing the power supply voltage to provide an input signal level (reference level) at which fC is desired to oscillate. Although it is difficult to make a resistor accurately in a semiconductor integrated circuit, it is possible to make a resistor with very high relative accuracy. A more accurate voltage source, such as a Zener diode reference voltage, may be connected to this terminal. Signals are extracted from different points inside the low-pass filter 217 and connected to the second input terminals 214 and 215 of the signal synthesis circuit for the first and second signals, and the resistor R4 is used to stabilize the PLL system. This resistance is not essentially different from that shown in FIG.
【0015】図2の構成を見ると抵抗R11〜R15、
コンデンサC11〜C13、水晶発振子Xを除けばすべ
てMOSトランジスタで構成されている。抵抗、コンデ
ンサは絶対精度が要求されることは無い。従って抵抗は
半導体集積回路に内臓できる。また必要とする発振周波
数のレンジによっても異なるがコンデンサC11も内臓
が可能であることが多い。低い周波数が必要なときは出
力端子216に分周回路を接続することにより、PLL
系は高い周波数で発振させておけばC1も小容量で済み
集積回路化が容易となる。Looking at the configuration of FIG. 2, the resistors R11 to R15,
All components except capacitors C11 to C13 and crystal oscillator X are composed of MOS transistors. Absolute precision is not required for resistors and capacitors. Therefore, the resistor can be built into the semiconductor integrated circuit. Further, although it depends on the required oscillation frequency range, it is often possible to incorporate the capacitor C11. When a low frequency is required, by connecting a frequency divider circuit to the output terminal 216, the PLL
If the system is made to oscillate at a high frequency, the capacitance of C1 can be reduced and it can be easily integrated into an integrated circuit.
【0016】以上述べた様に本発明によれば高精度部品
を用いることなくきわめて安定な電圧制御発振回路を実
現できる。高精度の部品を用いる必要が無いから半導体
集積回路化がきわめて容易となり実装上、製造上のメリ
ットが大きい。As described above, according to the present invention, an extremely stable voltage controlled oscillation circuit can be realized without using high precision components. Since there is no need to use high-precision parts, it is extremely easy to integrate semiconductor circuits, which has great advantages in terms of packaging and manufacturing.
【0017】本発明による例(図1,2)と従来例(図
3,4)を比較すると本発明の方がかなり複雑になって
おり従来例に比較してあまりメリットが無い様に思われ
るかも知れない。しかし事実は逆なのであって半導体集
積回路上に図2の回路を構成する場合そのチップ上に占
める面積はわずかである。図4の従来例の様に外付部品
を必要とするときは半導体集積回路上のボンディングパ
ッドの面積や出力トランジスタ(例えば図4のコンデン
サC1(外付)を駆動するP4,P5,N2,N3、抵
抗R1,R2(外付)を駆動するP1,N1)に大きな
ものが必要となりそれ等の占める面積の方が本発明の回
路に比べはるかに大きくなっているのである。また本発
明では水晶発振回路の様な安定な発振回路を必要とする
が、通常大規模集積回路では電圧制御発振回路の他に安
定な基準パルス列が必要な場合が多く、これと共用すれ
ば良いので本発明を実施するにあたって障害とはならな
い。また本発明では図1のノード116または117、
図2のノード218,219に直列な分周回路または周
波数変換回路を入れ、その分周比等を論理回路で制御す
ることにより同一の回路で任意にフリーラン周波数を設
定することができる。Comparing the example according to the present invention (FIGS. 1 and 2) and the conventional example (FIGS. 3 and 4), it appears that the present invention is considerably more complicated and does not have much advantage over the conventional example. May. However, the fact is the opposite; when the circuit of FIG. 2 is constructed on a semiconductor integrated circuit, the area occupied on the chip is small. When external components are required, as in the conventional example shown in FIG. , P1, N1) that drive the resistors R1, R2 (external) are required, and the area occupied by them is much larger than that of the circuit of the present invention. Furthermore, although the present invention requires a stable oscillation circuit such as a crystal oscillation circuit, in large-scale integrated circuits, a stable reference pulse train is often required in addition to the voltage-controlled oscillation circuit, and it is sufficient to use this in combination with the voltage-controlled oscillation circuit. Therefore, it does not pose an obstacle to implementing the present invention. Further, in the present invention, the node 116 or 117 in FIG.
By inserting a frequency dividing circuit or a frequency converting circuit in series with the nodes 218 and 219 in FIG. 2 and controlling the frequency division ratio and the like with a logic circuit, it is possible to arbitrarily set the free run frequency using the same circuit.
【0018】[0018]
【発明の効果】この様に本発明は集積回路の容易な電圧
制御発振回路を安定化する方法を示し、デジタル集積回
路にも容易に組込める電圧制御発振回路を示した。本発
明を実施すればコスト、実装スペースを減少でき機器を
実現していく上で大いに貢献できる。As described above, the present invention has shown a method for easily stabilizing a voltage controlled oscillation circuit in an integrated circuit, and has shown a voltage controlled oscillation circuit that can be easily incorporated into a digital integrated circuit. By implementing the present invention, costs and mounting space can be reduced and it can greatly contribute to the realization of devices.
【図1】[Figure 1]
【図2】本発明の実施例を示す図。FIG. 2 is a diagram showing an embodiment of the present invention.
【図3】[Figure 3]
【図4】従来の電圧制御発振回路を示す図である。FIG. 4 is a diagram showing a conventional voltage controlled oscillation circuit.
101,201…第1の信号合成回路
103,203…第2の信号合成回路
102,202…第1の電圧制御発振回路104,20
4…第2の電圧制御発振回路106,208…位相比較
回路
105,217…ローパスフィルタ
107,211…基準周波数発振回路
109,212…第1の信号合成回路の第1の入力端子
。制御端子
110,214…第1の信号合成回路の第2の入力端子
111,213…第2の信号合成回路の第1の入力端子
112,215…第2の信号合成回路の第2の入力端子
113,216…出力端子101, 201...First signal synthesis circuit 103, 203...Second signal synthesis circuit 102, 202...First voltage controlled oscillation circuit 104, 20
4...Second voltage controlled oscillation circuit 106, 208...Phase comparison circuit 105, 217...Low pass filter 107, 211...Reference frequency oscillation circuit 109, 212...First input terminal of the first signal synthesis circuit. Control terminals 110, 214...Second input terminals of the first signal synthesis circuit 111, 213...First input terminals of the second signal synthesis circuit 112, 215...Second input terminal of the second signal synthesis circuit 113,216...output terminal
Claims (1)
第2の端子(109,110)に与えられた信号を受け
てそれ等の信号を合成し出力する第1の手段−101 b.前記手段101と同じ特性を有する第2の手段−1
03 c.前記第1の信号合成手段101の信号により発振周
波数を制御される第1の発振回路−102d.前記発振
回路102と同じ特性を持ち前記第2の信号合成手段1
03の信号により制御される第2の発振回路−104 e.基準となる周波数の信号を発する手段−107を有
し、前記第2の発振回路104の出力は前記基準となる
周波数の信号を発する手段107より発せられる信号と
位相を比較し、その結果により前記第2の発振回路10
4の出力周波数を調整すべく前記第2の信号合成手段1
03の第2の入力端子112に信号を加える。また前記
第2の信号合成手段103の第1の入力端子111には
基準レベルとなるレベル信号を与え前記第1の信号合成
手段101の第2の入力端子110には前記第2の信号
合成手段103の第2の入力端子112に印加される信
号を与える。さらに前記第1の信号合成手段101の第
1の入力端子109を制御端子、第一の発振回路102
の出力を出力とすることを特徴とする電圧制御発振回路
。Claim 1: At least the following constituent requirements a. 1st,
First means-101 for receiving signals applied to second terminals (109, 110), synthesizing and outputting the signals; b. Second means-1 having the same characteristics as the means 101
03 c. a first oscillation circuit whose oscillation frequency is controlled by the signal of the first signal synthesis means 101-102d. The second signal synthesis means 1 has the same characteristics as the oscillation circuit 102.
Second oscillation circuit controlled by signal 03-104 e. The output of the second oscillation circuit 104 is compared in phase with the signal emitted from the reference frequency signal 107, and based on the result, the output of the second oscillation circuit 104 is Second oscillation circuit 10
the second signal synthesizing means 1 to adjust the output frequency of 4;
A signal is applied to the second input terminal 112 of 03. Further, a level signal serving as a reference level is supplied to the first input terminal 111 of the second signal synthesizing means 103, and the second input terminal 110 of the first signal synthesizing means 101 is connected to the second signal synthesizing means. 103 provides a signal to be applied to a second input terminal 112 of 103 . Further, the first input terminal 109 of the first signal synthesizing means 101 is used as a control terminal, and the first oscillation circuit 102
A voltage controlled oscillator circuit characterized in that the output is an output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3018748A JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3018748A JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57136684A Division JPS5927615A (en) | 1982-08-05 | 1982-08-05 | Voltage controlled oscillating circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8155247A Division JP2737747B2 (en) | 1996-06-17 | 1996-06-17 | Voltage controlled oscillator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04211519A true JPH04211519A (en) | 1992-08-03 |
JPH0770999B2 JPH0770999B2 (en) | 1995-07-31 |
Family
ID=11980274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3018748A Expired - Lifetime JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0770999B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4131861A (en) * | 1977-12-30 | 1978-12-26 | International Business Machines Corporation | Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop |
JPS5615128U (en) * | 1979-07-13 | 1981-02-09 | ||
JPS56138337A (en) * | 1980-02-28 | 1981-10-28 | Gen Electric | Frequency converter and phase locked loop circuit |
-
1991
- 1991-02-12 JP JP3018748A patent/JPH0770999B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4131861A (en) * | 1977-12-30 | 1978-12-26 | International Business Machines Corporation | Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop |
JPS5615128U (en) * | 1979-07-13 | 1981-02-09 | ||
JPS56138337A (en) * | 1980-02-28 | 1981-10-28 | Gen Electric | Frequency converter and phase locked loop circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0770999B2 (en) | 1995-07-31 |
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