JPS56137980A - Verifying method for set of types - Google Patents

Verifying method for set of types

Info

Publication number
JPS56137980A
JPS56137980A JP4172580A JP4172580A JPS56137980A JP S56137980 A JPS56137980 A JP S56137980A JP 4172580 A JP4172580 A JP 4172580A JP 4172580 A JP4172580 A JP 4172580A JP S56137980 A JPS56137980 A JP S56137980A
Authority
JP
Japan
Prior art keywords
type
code
sort
content
discrimination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4172580A
Other languages
Japanese (ja)
Inventor
Tadashi Sato
Nobuo Ushiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4172580A priority Critical patent/JPS56137980A/en
Publication of JPS56137980A publication Critical patent/JPS56137980A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To verify the appropriateness of the sort of a replaced type set by providing a projected part for generating a code pulse for discrimination of the type set between projected parts for generating type clock and by reading the code pulse for discrimination of the type set.
CONSTITUTION: When a type belt 4 is replaced, a code indicating the sort thereof is set in a register REG. The content of setting in this register REG is compared with the content of a shift register SREG wherein the code for discrimination of the type belt in a comparison circuit COM2 and the result of accordance or discordance is displayed in a displaying device DSP. According to the content of this display, it can be verified whether a type belt of a proper sort is mounted or not. Also, in the case when a type code to be set in a universal character set buffer UCSB is designated, the sort code of the type belt corresponding to the type code is set in the register REG, whereby the presence of false operation can be verified immediately through the content of display of the displaying device DSP.
COPYRIGHT: (C)1981,JPO&Japio
JP4172580A 1980-03-31 1980-03-31 Verifying method for set of types Pending JPS56137980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4172580A JPS56137980A (en) 1980-03-31 1980-03-31 Verifying method for set of types

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4172580A JPS56137980A (en) 1980-03-31 1980-03-31 Verifying method for set of types

Publications (1)

Publication Number Publication Date
JPS56137980A true JPS56137980A (en) 1981-10-28

Family

ID=12616389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4172580A Pending JPS56137980A (en) 1980-03-31 1980-03-31 Verifying method for set of types

Country Status (1)

Country Link
JP (1) JPS56137980A (en)

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