JPS56137749A - Synchronism establishment system - Google Patents
Synchronism establishment systemInfo
- Publication number
- JPS56137749A JPS56137749A JP4090180A JP4090180A JPS56137749A JP S56137749 A JPS56137749 A JP S56137749A JP 4090180 A JP4090180 A JP 4090180A JP 4090180 A JP4090180 A JP 4090180A JP S56137749 A JPS56137749 A JP S56137749A
- Authority
- JP
- Japan
- Prior art keywords
- held
- circuit
- low level
- output
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To reduce power consumption when communication is intermitted by eliminating the need for burst communication for holding the synchronism between a master device and subordinate device when the communication is intermitted and by activating only a circuit which detects the reception of an origination request signal and a synchronizing circuit at the subordinate device side. CONSTITUTION:After end information of signal bits is transmitted, the output of origination control circuit 26 is held at the low level with control signal 31. Line driver 21 is disabled and line receiver 22 is enabled at any time and held in standby. Subscriber's circuit 10, on the other hand, holds the output of transmission control circuit 17 at the low level with control signal 7 simultaneously with the reception of the end information from digital subscriber's terminal 20. The output of gate 18 is held at the low level and while line driver 11 is disabled, line receiver 12 is enabled at any time and held in standby.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4090180A JPS56137749A (en) | 1980-03-28 | 1980-03-28 | Synchronism establishment system |
US06/245,281 US4404672A (en) | 1980-03-28 | 1981-03-19 | Subscriber terminal for use in a time shared bidirectional digital communication network |
DE8181102349T DE3171775D1 (en) | 1980-03-28 | 1981-03-27 | Subscriber terminal for use in a time shared bidirectional digital communication network |
EP81102349A EP0037107B1 (en) | 1980-03-28 | 1981-03-27 | Subscriber terminal for use in a time shared bidirectional digital communication network |
AU68841/81A AU537975B2 (en) | 1980-03-28 | 1981-03-27 | Subscriber terminal for digital network |
CA000374013A CA1163734A (en) | 1980-03-28 | 1981-03-27 | Subscriber terminal for use in a time shared bidirectional digital communication network |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4090180A JPS56137749A (en) | 1980-03-28 | 1980-03-28 | Synchronism establishment system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56137749A true JPS56137749A (en) | 1981-10-27 |
JPH0361384B2 JPH0361384B2 (en) | 1991-09-19 |
Family
ID=12593407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4090180A Granted JPS56137749A (en) | 1980-03-28 | 1980-03-28 | Synchronism establishment system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56137749A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS528716A (en) * | 1975-07-11 | 1977-01-22 | Chiba Tsushin Kogyo Kk | Synchronous system in simultaneous communication |
JPS53148937A (en) * | 1977-06-01 | 1978-12-26 | Hitachi Ltd | Data transfer system |
JPS5424506A (en) * | 1977-07-26 | 1979-02-23 | Hitachi Ltd | Modem control unit of semi-double type |
-
1980
- 1980-03-28 JP JP4090180A patent/JPS56137749A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS528716A (en) * | 1975-07-11 | 1977-01-22 | Chiba Tsushin Kogyo Kk | Synchronous system in simultaneous communication |
JPS53148937A (en) * | 1977-06-01 | 1978-12-26 | Hitachi Ltd | Data transfer system |
JPS5424506A (en) * | 1977-07-26 | 1979-02-23 | Hitachi Ltd | Modem control unit of semi-double type |
Also Published As
Publication number | Publication date |
---|---|
JPH0361384B2 (en) | 1991-09-19 |
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