JPS56136009A - Amplifying circuit for charge transfer device - Google Patents

Amplifying circuit for charge transfer device

Info

Publication number
JPS56136009A
JPS56136009A JP3990080A JP3990080A JPS56136009A JP S56136009 A JPS56136009 A JP S56136009A JP 3990080 A JP3990080 A JP 3990080A JP 3990080 A JP3990080 A JP 3990080A JP S56136009 A JPS56136009 A JP S56136009A
Authority
JP
Japan
Prior art keywords
most1
amplifying circuit
amplifying
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3990080A
Other languages
Japanese (ja)
Inventor
Yoshihiro Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3990080A priority Critical patent/JPS56136009A/en
Publication of JPS56136009A publication Critical patent/JPS56136009A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an amplifying circuit for CTD which can easily be integrated with CTD and has an adequate DC component suppressing function, by utilizing the triode operation range of amplifying MOST.
CONSTITUTION: Once signal charge enters output diode 8 of CTDb, resetting MOST5 turns off. As the junction capacitor of output diode 8 is charged, gate G of amplifying MOST1 drops in potential to generate an input signal to amplifying circuit (a). When the input voltage is expressed by the ordinate and the output voltage by the abscissa, the gradient showing the degree of amplification is shown by curve K. In region (c) of this curve K, MOST1 enters the triode operation region and while the gate mutual conductance does not increase much, the degree of amplification decreases suddenly. For this porpose, the amplitude of a signal voltage energizing the gate terminal of MOST1 is set a little bit beyond region (c), so that a DC component based upon the background light of the input signal can greatly by suppressed.
COPYRIGHT: (C)1981,JPO&Japio
JP3990080A 1980-03-27 1980-03-27 Amplifying circuit for charge transfer device Pending JPS56136009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3990080A JPS56136009A (en) 1980-03-27 1980-03-27 Amplifying circuit for charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3990080A JPS56136009A (en) 1980-03-27 1980-03-27 Amplifying circuit for charge transfer device

Publications (1)

Publication Number Publication Date
JPS56136009A true JPS56136009A (en) 1981-10-23

Family

ID=12565829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3990080A Pending JPS56136009A (en) 1980-03-27 1980-03-27 Amplifying circuit for charge transfer device

Country Status (1)

Country Link
JP (1) JPS56136009A (en)

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