JPS56134848A - Noise reduction circuit - Google Patents
Noise reduction circuitInfo
- Publication number
- JPS56134848A JPS56134848A JP3711180A JP3711180A JPS56134848A JP S56134848 A JPS56134848 A JP S56134848A JP 3711180 A JP3711180 A JP 3711180A JP 3711180 A JP3711180 A JP 3711180A JP S56134848 A JPS56134848 A JP S56134848A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- control circuit
- input
- gain control
- switched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G9/00—Combinations of two or more types of control, e.g. gain control and tone control
- H03G9/02—Combinations of two or more types of control, e.g. gain control and tone control in untuned amplifiers
- H03G9/025—Combinations of two or more types of control, e.g. gain control and tone control in untuned amplifiers frequency-dependent volume compression or expansion, e.g. multiple-band systems
Abstract
PURPOSE:To enhance the reduction effect of noise modulation, by enlarging the compression ratio only for the high band of the input audio signal and by preventing needless compression and expansion from being performed for the middle band and the low band. CONSTITUTION:Gain control circuit 20 performs the decoding operation where the audio signal from input terminal 16 has the level expanded mainly. When change- over switch 13 is switched to terminal (d), amplifier 14 amplifies the input signal from input terminal 11 and sends it to input terminal 16 of gain control circuit 20, and the decoded signal is obtained through output terminal 17 from decoding output terminal 12d. When change-over switch 13 is switched to terminal (e), the encoding characteristic is obtained in gain control circuit 20.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3711180A JPS56134848A (en) | 1980-03-24 | 1980-03-24 | Noise reduction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3711180A JPS56134848A (en) | 1980-03-24 | 1980-03-24 | Noise reduction circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56134848A true JPS56134848A (en) | 1981-10-21 |
JPS6316052B2 JPS6316052B2 (en) | 1988-04-07 |
Family
ID=12488480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3711180A Granted JPS56134848A (en) | 1980-03-24 | 1980-03-24 | Noise reduction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56134848A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5951630A (en) * | 1982-09-17 | 1984-03-26 | Sony Corp | Dynamic range compression circuit |
EP0130613A2 (en) * | 1983-07-04 | 1985-01-09 | Victor Company Of Japan, Limited | Noise reduction circuit |
-
1980
- 1980-03-24 JP JP3711180A patent/JPS56134848A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5951630A (en) * | 1982-09-17 | 1984-03-26 | Sony Corp | Dynamic range compression circuit |
JPH0522416B2 (en) * | 1982-09-17 | 1993-03-29 | Sony Corp | |
EP0130613A2 (en) * | 1983-07-04 | 1985-01-09 | Victor Company Of Japan, Limited | Noise reduction circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6316052B2 (en) | 1988-04-07 |
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