JPS56128019A - Parallel analog-digital converting circuit - Google Patents

Parallel analog-digital converting circuit

Info

Publication number
JPS56128019A
JPS56128019A JP3025280A JP3025280A JPS56128019A JP S56128019 A JPS56128019 A JP S56128019A JP 3025280 A JP3025280 A JP 3025280A JP 3025280 A JP3025280 A JP 3025280A JP S56128019 A JPS56128019 A JP S56128019A
Authority
JP
Japan
Prior art keywords
circuits
sampling
sampling pulse
converting circuit
digital converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3025280A
Other languages
Japanese (ja)
Inventor
Masayasu Miyake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP3025280A priority Critical patent/JPS56128019A/en
Publication of JPS56128019A publication Critical patent/JPS56128019A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To easily manufacture an A/D converter at a low cost by combining an A/D converter together with a presampling hold circuit provided in series to it, making one pair, and connecting plural pairs in parallel. CONSTITUTION:The sampling hold circuits 1, 3 are provided in front of the A/D converters 2, 4, respectively. The outputs of the circuits 2, 4 become a digital signal dk which has been converted through the OR gate 5. On the other hand, the sampling pulse train is converted to two sampling pulse trains (c), (d) of every other train, and an analog signal (a) is sampled and held by each sampling pulse train in the circuits 1, 3. Accordingly, the sampling frequency can be raised, and A/D conversion can be executed at a high speed.
JP3025280A 1980-03-12 1980-03-12 Parallel analog-digital converting circuit Pending JPS56128019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3025280A JPS56128019A (en) 1980-03-12 1980-03-12 Parallel analog-digital converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3025280A JPS56128019A (en) 1980-03-12 1980-03-12 Parallel analog-digital converting circuit

Publications (1)

Publication Number Publication Date
JPS56128019A true JPS56128019A (en) 1981-10-07

Family

ID=12298513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3025280A Pending JPS56128019A (en) 1980-03-12 1980-03-12 Parallel analog-digital converting circuit

Country Status (1)

Country Link
JP (1) JPS56128019A (en)

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