JPS56121149A - Microprogram control equipment - Google Patents
Microprogram control equipmentInfo
- Publication number
- JPS56121149A JPS56121149A JP2441980A JP2441980A JPS56121149A JP S56121149 A JPS56121149 A JP S56121149A JP 2441980 A JP2441980 A JP 2441980A JP 2441980 A JP2441980 A JP 2441980A JP S56121149 A JPS56121149 A JP S56121149A
- Authority
- JP
- Japan
- Prior art keywords
- address
- register
- generating part
- selector
- high speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
- G06F9/265—Microinstruction selection based on results of processing by address selection on input of storage
Abstract
PURPOSE:To execute the processing at a high speed by providing an address generating memory device storing a data which has added ''1'' to the address, independently from the control memory device. CONSTITUTION:When the microaddress showing the address A is outputted by the selector 12, this address is in put in common to the control memory device 11 and the address generating part 21. As a result, the corresponding microinstruction is read out from the address A of the device 11, and also a data showing the address A+1 is read out from the address A of the address generating part 21. The read-out outputs of the device 11 and the generating part 21 are retained in the microinstruction register 14 and the address register 16, respectively, by the timing of a machine clock signal MCLK. In a normal state, the register 16 is selected by the selector 12, and on the other hand, in case when the register 14 is a branch instruction, the branch address is selected by the selector 12, and both of them are output to the address line 13. In this way, the processing can be executed at a high speed by using a device 11 and a generating part 21, consisting of high speed memory elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2441980A JPS56121149A (en) | 1980-02-28 | 1980-02-28 | Microprogram control equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2441980A JPS56121149A (en) | 1980-02-28 | 1980-02-28 | Microprogram control equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56121149A true JPS56121149A (en) | 1981-09-22 |
Family
ID=12137627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2441980A Pending JPS56121149A (en) | 1980-02-28 | 1980-02-28 | Microprogram control equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56121149A (en) |
-
1980
- 1980-02-28 JP JP2441980A patent/JPS56121149A/en active Pending
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