JPS56120237A - Line identifying system - Google Patents

Line identifying system

Info

Publication number
JPS56120237A
JPS56120237A JP2366080A JP2366080A JPS56120237A JP S56120237 A JPS56120237 A JP S56120237A JP 2366080 A JP2366080 A JP 2366080A JP 2366080 A JP2366080 A JP 2366080A JP S56120237 A JPS56120237 A JP S56120237A
Authority
JP
Japan
Prior art keywords
channel
virtual random
delay circuit
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2366080A
Other languages
Japanese (ja)
Other versions
JPH023575B2 (en
Inventor
Toshiyuki Morita
Masao Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2366080A priority Critical patent/JPS56120237A/en
Publication of JPS56120237A publication Critical patent/JPS56120237A/en
Publication of JPH023575B2 publication Critical patent/JPH023575B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Radio Relay Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To enable line identification, by making different the virtual random signal applied to other channel by a given phase, to the virtual random signal applied to the reference channel. CONSTITUTION:The signal inserted with the frame synchronising signal FS and converted in speed is separated into two systems with a serial-parallel conversion circuit SP. Further, one channel is scrambled with the virtual random signal generator PN1 at a scramble circuit SCR1. Other channel is scrambled with the signal delayed at a delay circuit DL1. Further, by keeping the delay time between the delay circuit DL1 at the transmission side and the delay circuit DL2 at the reception side equal each other, reception and reproduction can be made for correct line only.
JP2366080A 1980-02-27 1980-02-27 Line identifying system Granted JPS56120237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2366080A JPS56120237A (en) 1980-02-27 1980-02-27 Line identifying system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2366080A JPS56120237A (en) 1980-02-27 1980-02-27 Line identifying system

Publications (2)

Publication Number Publication Date
JPS56120237A true JPS56120237A (en) 1981-09-21
JPH023575B2 JPH023575B2 (en) 1990-01-24

Family

ID=12116653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2366080A Granted JPS56120237A (en) 1980-02-27 1980-02-27 Line identifying system

Country Status (1)

Country Link
JP (1) JPS56120237A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137344A (en) * 1982-02-09 1983-08-15 Nec Corp Route discrimination signal generating circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120620A (en) * 1974-08-14 1976-02-19 Nippon Electric Co
JPS5366318A (en) * 1976-11-26 1978-06-13 Fujitsu Ltd Scramble system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120620A (en) * 1974-08-14 1976-02-19 Nippon Electric Co
JPS5366318A (en) * 1976-11-26 1978-06-13 Fujitsu Ltd Scramble system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137344A (en) * 1982-02-09 1983-08-15 Nec Corp Route discrimination signal generating circuit

Also Published As

Publication number Publication date
JPH023575B2 (en) 1990-01-24

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