JPS5366318A - Scramble system - Google Patents

Scramble system

Info

Publication number
JPS5366318A
JPS5366318A JP14266476A JP14266476A JPS5366318A JP S5366318 A JPS5366318 A JP S5366318A JP 14266476 A JP14266476 A JP 14266476A JP 14266476 A JP14266476 A JP 14266476A JP S5366318 A JPS5366318 A JP S5366318A
Authority
JP
Japan
Prior art keywords
scramble system
circuit
inhibit pulse
omitting
offer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14266476A
Other languages
Japanese (ja)
Other versions
JPS573254B2 (en
Inventor
Shinichi Kuriaki
Kazuo Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14266476A priority Critical patent/JPS5366318A/en
Publication of JPS5366318A publication Critical patent/JPS5366318A/en
Publication of JPS573254B2 publication Critical patent/JPS573254B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To offer the system scrambling the information signal with an easy means, by omitting the circuit for inhibit pulse formation and the circuit synthesizing pseudo noise and inhibit pulse.
JP14266476A 1976-11-26 1976-11-26 Scramble system Granted JPS5366318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14266476A JPS5366318A (en) 1976-11-26 1976-11-26 Scramble system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14266476A JPS5366318A (en) 1976-11-26 1976-11-26 Scramble system

Publications (2)

Publication Number Publication Date
JPS5366318A true JPS5366318A (en) 1978-06-13
JPS573254B2 JPS573254B2 (en) 1982-01-20

Family

ID=15320615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14266476A Granted JPS5366318A (en) 1976-11-26 1976-11-26 Scramble system

Country Status (1)

Country Link
JP (1) JPS5366318A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56120237A (en) * 1980-02-27 1981-09-21 Fujitsu Ltd Line identifying system
JPS56125133A (en) * 1980-03-06 1981-10-01 Nippon Telegr & Teleph Corp <Ntt> Scramble system
JPS56131725U (en) * 1980-03-04 1981-10-06

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0295634U (en) * 1989-01-11 1990-07-30

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56120237A (en) * 1980-02-27 1981-09-21 Fujitsu Ltd Line identifying system
JPH023575B2 (en) * 1980-02-27 1990-01-24 Fujitsu Ltd
JPS56131725U (en) * 1980-03-04 1981-10-06
JPS56125133A (en) * 1980-03-06 1981-10-01 Nippon Telegr & Teleph Corp <Ntt> Scramble system

Also Published As

Publication number Publication date
JPS573254B2 (en) 1982-01-20

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