JPS56100532A - Automatic gain control device - Google Patents
Automatic gain control deviceInfo
- Publication number
- JPS56100532A JPS56100532A JP394080A JP394080A JPS56100532A JP S56100532 A JPS56100532 A JP S56100532A JP 394080 A JP394080 A JP 394080A JP 394080 A JP394080 A JP 394080A JP S56100532 A JPS56100532 A JP S56100532A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- amplifier
- level
- input
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 abstract 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To make leading-in of the automatic gain control device stable, sure, and high-speed, by making the input signal range optimum by the amplification degree corresponding to the input signal level and by holding the control voltage of the amplifier in a certain level for no input. CONSTITUTION:Level detector 8 is operated according to output (b) of carrier detector 5 to detect the maximum level of input singal (a) and assignes it to a prescribed amplifier of amplifier group 9 for amplification or attenuation of signal (a), and the selected amplifier of amplifier group 9 amplifies or attenuates signal (a) to generate input signal (a') and outputs this signal. Oscillator 6 generates the signal of a prescribed level or less and is operated in respons to signal (b) of detector 5. Consequently, adder 7 sends only one of input signal (a) of the prescribed level or more and initializing signal (e) to voltage control amplifier 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP394080A JPS5854535B2 (en) | 1980-01-17 | 1980-01-17 | automatic gain control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP394080A JPS5854535B2 (en) | 1980-01-17 | 1980-01-17 | automatic gain control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56100532A true JPS56100532A (en) | 1981-08-12 |
JPS5854535B2 JPS5854535B2 (en) | 1983-12-05 |
Family
ID=11571120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP394080A Expired JPS5854535B2 (en) | 1980-01-17 | 1980-01-17 | automatic gain control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5854535B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6057242U (en) * | 1983-09-26 | 1985-04-22 | カシオ計算機株式会社 | data receiving circuit |
JPS61103941U (en) * | 1984-12-12 | 1986-07-02 | ||
JPS6447134A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Agc circuit |
-
1980
- 1980-01-17 JP JP394080A patent/JPS5854535B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6057242U (en) * | 1983-09-26 | 1985-04-22 | カシオ計算機株式会社 | data receiving circuit |
JPS61103941U (en) * | 1984-12-12 | 1986-07-02 | ||
JPS6447134A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Agc circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5854535B2 (en) | 1983-12-05 |
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