JPS5599895A - Terminal control system - Google Patents
Terminal control systemInfo
- Publication number
- JPS5599895A JPS5599895A JP750679A JP750679A JPS5599895A JP S5599895 A JPS5599895 A JP S5599895A JP 750679 A JP750679 A JP 750679A JP 750679 A JP750679 A JP 750679A JP S5599895 A JPS5599895 A JP S5599895A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- failure
- fed
- circuits
- ad4n
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
- H04Q9/08—Calling by using continuous ac
- H04Q9/12—Calling by using continuous ac using combinations of frequencies
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Selective Calling Equipment (AREA)
Abstract
PURPOSE:To prevent malfunction by stopping the operation of terminal unit, when failure in the time length of each frequency, failure in arrangement of frequency or duplication of frequency is detected, after the discrimination of frequency at terminals. CONSTITUTION:In controlling terminals by selecting the operation items of terminal and terminal itself with the combination of frequencies through and delivery of serial signal of a plurality of frequencies from the monitor control station to a plurality of terminals, the discrimination of frequency is made with BPF1-BPF3n, and level detection and A/D conversion are made with the detectors DET1- DET3n. The output of the detectors DET1 and DET2 is fed to the circuit combining the logic circuit and delay circut or the like to detect the time length, arrangement and duplication of frequency. If failure, alarm signal is fed to the AND circuits AD41-AD4n. Further, the output of the detectors DET31-DET3n is fed to the circuit combining delay circuits to detect the failure in frequency against operation items, and it is fed to the circuits AD41-AD4n, and the operation of the unit is stopped with the output of the circuits AD41-AD4n.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP750679A JPS5599895A (en) | 1979-01-24 | 1979-01-24 | Terminal control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP750679A JPS5599895A (en) | 1979-01-24 | 1979-01-24 | Terminal control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5599895A true JPS5599895A (en) | 1980-07-30 |
JPS6221440B2 JPS6221440B2 (en) | 1987-05-12 |
Family
ID=11667663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP750679A Granted JPS5599895A (en) | 1979-01-24 | 1979-01-24 | Terminal control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5599895A (en) |
-
1979
- 1979-01-24 JP JP750679A patent/JPS5599895A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6221440B2 (en) | 1987-05-12 |
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