JPS55949A - Video display controller - Google Patents

Video display controller

Info

Publication number
JPS55949A
JPS55949A JP7400178A JP7400178A JPS55949A JP S55949 A JPS55949 A JP S55949A JP 7400178 A JP7400178 A JP 7400178A JP 7400178 A JP7400178 A JP 7400178A JP S55949 A JPS55949 A JP S55949A
Authority
JP
Japan
Prior art keywords
signal
crt
channel
crts
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7400178A
Other languages
Japanese (ja)
Inventor
Kenkichi Hihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7400178A priority Critical patent/JPS55949A/en
Publication of JPS55949A publication Critical patent/JPS55949A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To prevent a screen position shift even if several CRTs are connected, by providing a correcting method which equalizes timings between a synchronizing signal and video signal supplied to each CRT as to all CRT.
CONSTITUTION: In the video display controller which controls several CRTs with different display contents by itself, access to a dot pattern signal from character generator CG is attained within one character display cycle in a time division mode and it is assigned to dot registers 7 and 8 of the channel of each CRT. To the output of register 7, delay circuit 31 is connected which delays the signal by a time difference with the output time to register 8, and the common synchronizing signal of both channels and video signal of each channel are inputted to mixer circuits 11 and 12. Consequently, the timing between the synchronizing signal and video signal of each channel can be equalized and the display screen position shift between CRTs 13 and 14 can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP7400178A 1978-06-19 1978-06-19 Video display controller Pending JPS55949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7400178A JPS55949A (en) 1978-06-19 1978-06-19 Video display controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7400178A JPS55949A (en) 1978-06-19 1978-06-19 Video display controller

Publications (1)

Publication Number Publication Date
JPS55949A true JPS55949A (en) 1980-01-07

Family

ID=13534390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7400178A Pending JPS55949A (en) 1978-06-19 1978-06-19 Video display controller

Country Status (1)

Country Link
JP (1) JPS55949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61253979A (en) * 1985-05-02 1986-11-11 Matsushita Electric Ind Co Ltd Rotary head type magnetic picture recording and reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61253979A (en) * 1985-05-02 1986-11-11 Matsushita Electric Ind Co Ltd Rotary head type magnetic picture recording and reproducing device

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