JPS5492023A - Letter signal generating device - Google Patents

Letter signal generating device

Info

Publication number
JPS5492023A
JPS5492023A JP15777077A JP15777077A JPS5492023A JP S5492023 A JPS5492023 A JP S5492023A JP 15777077 A JP15777077 A JP 15777077A JP 15777077 A JP15777077 A JP 15777077A JP S5492023 A JPS5492023 A JP S5492023A
Authority
JP
Japan
Prior art keywords
signal
circuit
letter
dot
delayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15777077A
Other languages
Japanese (ja)
Inventor
Tsutomu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP15777077A priority Critical patent/JPS5492023A/en
Publication of JPS5492023A publication Critical patent/JPS5492023A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To display easily readable letters by making new letter signals by obtaining "OR" signal of the letter signal and the delay signal which has delayed letter signals, elongating dots in the scan direction and strengthening the connection between dots adjacent in the diagonal direction.
CONSTITUTION: With the letter signal producing system that displays letters on CRT 6 in dot pattern having been scanned by providing display memory 1, character generater 3, timing control circuit 2 and parallel serial conversion circuit 4, serial dot signal f from circuit 4 is applied to one of the inputs of OR circuit 8 as well as delay elment 7 and, then, dot signal g that has been delayed by delay element 7 is applied to the other input of circuit 8. Dot signal f and delayed dot signal g are processed through "OR" circuit 8 to newly produced dot signal h and, then, dot signal h is applied to CRT 6 through luminance modulation circuit 5, thus strengthening the connection between diagonally adjacent dots and displaying letter more clearly.
COPYRIGHT: (C)1979,JPO&Japio
JP15777077A 1977-12-29 1977-12-29 Letter signal generating device Pending JPS5492023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15777077A JPS5492023A (en) 1977-12-29 1977-12-29 Letter signal generating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15777077A JPS5492023A (en) 1977-12-29 1977-12-29 Letter signal generating device

Publications (1)

Publication Number Publication Date
JPS5492023A true JPS5492023A (en) 1979-07-20

Family

ID=15656917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15777077A Pending JPS5492023A (en) 1977-12-29 1977-12-29 Letter signal generating device

Country Status (1)

Country Link
JP (1) JPS5492023A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767988A (en) * 1980-10-15 1982-04-24 Mitsubishi Electric Corp Video display unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767988A (en) * 1980-10-15 1982-04-24 Mitsubishi Electric Corp Video display unit

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