JPS559268A - Digital display unit - Google Patents

Digital display unit

Info

Publication number
JPS559268A
JPS559268A JP8158278A JP8158278A JPS559268A JP S559268 A JPS559268 A JP S559268A JP 8158278 A JP8158278 A JP 8158278A JP 8158278 A JP8158278 A JP 8158278A JP S559268 A JPS559268 A JP S559268A
Authority
JP
Japan
Prior art keywords
display timing
digit
display
content
taken
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8158278A
Other languages
Japanese (ja)
Inventor
Takayoshi Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8158278A priority Critical patent/JPS559268A/en
Publication of JPS559268A publication Critical patent/JPS559268A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize the zero suppression function and to execute the shift right easily, by comparing the contents W and R of the wirte-in and readout address register, and taking W=R as the uppermost digit display timing and inhibiting the display with W≤R.
CONSTITUTION: The write-in address register WAR adds 1 to the content every time new data is given, and the readout address register RAR subtracts 1 from the content every time the display timing pulse is delivered. The magnitude of the content W of the register WAR and the content R of the register RAR is compared. The uppermost digit display timing is taken when W=R, and the display timing in the next order is taken as the lowermost digit display timing, the display timing after that is taken from the display timing for each digit from the lowermost digit to the uppermost rank digit sequentially. If the result of comparison is W≤R, the display of the display unit is inhibited. Thus, zero-suppression function is inhibited with a simple constitution and shift right can easily be made.
COPYRIGHT: (C)1980,JPO&Japio
JP8158278A 1978-07-04 1978-07-04 Digital display unit Pending JPS559268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8158278A JPS559268A (en) 1978-07-04 1978-07-04 Digital display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8158278A JPS559268A (en) 1978-07-04 1978-07-04 Digital display unit

Publications (1)

Publication Number Publication Date
JPS559268A true JPS559268A (en) 1980-01-23

Family

ID=13750303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8158278A Pending JPS559268A (en) 1978-07-04 1978-07-04 Digital display unit

Country Status (1)

Country Link
JP (1) JPS559268A (en)

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