JPS5591032A - Information processor which varies interruption request destination via interruption rejection signal - Google Patents

Information processor which varies interruption request destination via interruption rejection signal

Info

Publication number
JPS5591032A
JPS5591032A JP16103678A JP16103678A JPS5591032A JP S5591032 A JPS5591032 A JP S5591032A JP 16103678 A JP16103678 A JP 16103678A JP 16103678 A JP16103678 A JP 16103678A JP S5591032 A JPS5591032 A JP S5591032A
Authority
JP
Japan
Prior art keywords
interruption
signal
request
varies
request destination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16103678A
Other languages
Japanese (ja)
Inventor
Yoshio Hamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16103678A priority Critical patent/JPS5591032A/en
Publication of JPS5591032A publication Critical patent/JPS5591032A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize reduction of the interruption acceptance queuing time via the simple circuit by withdrawing the request for the interruption rejection signal received and then giving newly the interruption request to other device.
CONSTITUTION: Interruption request signal 31 of device 3 sets flip-flop (FF) 33, and interruption request signal 11 or 21 is delivered to device 1 or 2 according to the state of interruption request destination memory FF37. Now if signal 11 is delivered to device 1 via output 44 of FF37 with interruption acceptance signal 12 applied from device 1, FF33 is reset to carry out the interruption process. While with supply of interruption rejecton signal 13, signal 11 is discontinued with inversion given to FF37, and signal 21 is emitted to device 2. Interruption propriety signal 22 and 23 given from device 2 are processed in the same way as signals 12 and 13.
COPYRIGHT: (C)1980,JPO&Japio
JP16103678A 1978-12-28 1978-12-28 Information processor which varies interruption request destination via interruption rejection signal Pending JPS5591032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16103678A JPS5591032A (en) 1978-12-28 1978-12-28 Information processor which varies interruption request destination via interruption rejection signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16103678A JPS5591032A (en) 1978-12-28 1978-12-28 Information processor which varies interruption request destination via interruption rejection signal

Publications (1)

Publication Number Publication Date
JPS5591032A true JPS5591032A (en) 1980-07-10

Family

ID=15727367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16103678A Pending JPS5591032A (en) 1978-12-28 1978-12-28 Information processor which varies interruption request destination via interruption rejection signal

Country Status (1)

Country Link
JP (1) JPS5591032A (en)

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