JPS5591023A - Data display unit - Google Patents

Data display unit

Info

Publication number
JPS5591023A
JPS5591023A JP16184978A JP16184978A JPS5591023A JP S5591023 A JPS5591023 A JP S5591023A JP 16184978 A JP16184978 A JP 16184978A JP 16184978 A JP16184978 A JP 16184978A JP S5591023 A JPS5591023 A JP S5591023A
Authority
JP
Japan
Prior art keywords
signals
characters
frames
succeeding
resolution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16184978A
Other languages
Japanese (ja)
Inventor
Akira Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Gen Co Ltd
Original Assignee
Fujitsu General Ltd
Gen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gen Co Ltd filed Critical Fujitsu General Ltd
Priority to JP16184978A priority Critical patent/JPS5591023A/en
Publication of JPS5591023A publication Critical patent/JPS5591023A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To increase the number of characters in one line and thus enhance the resolution by completing the characters to be displayed via the interlace switching circuit and with succeeding n-units of frames.
CONSTITUTION: The strobe signals are generated at interlace switching circuit 12 alternately and every frame, and the bits are sampled every second position via the strobe signals for the input signals sent from parallel-serial conversion circuit 5. Then only the signals existing at the odd-numbered positions are extracted at the odd frames among the output signals of circuit 12, and only the signals existing at the even-numbered positions are extracted at even frames respectively. These output are then mixed 6 with the synchronous signals of then receive high frequency modulation 8, and the characters completed by the succeeding two frames are displayed on TV picture receiver 9. Thus the number of characters can be increased per line, as a result enhancing the resolution.
COPYRIGHT: (C)1980,JPO&Japio
JP16184978A 1978-12-29 1978-12-29 Data display unit Pending JPS5591023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16184978A JPS5591023A (en) 1978-12-29 1978-12-29 Data display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16184978A JPS5591023A (en) 1978-12-29 1978-12-29 Data display unit

Publications (1)

Publication Number Publication Date
JPS5591023A true JPS5591023A (en) 1980-07-10

Family

ID=15743102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16184978A Pending JPS5591023A (en) 1978-12-29 1978-12-29 Data display unit

Country Status (1)

Country Link
JP (1) JPS5591023A (en)

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