JPS5578664A - Facsimile receiver - Google Patents

Facsimile receiver

Info

Publication number
JPS5578664A
JPS5578664A JP15291678A JP15291678A JPS5578664A JP S5578664 A JPS5578664 A JP S5578664A JP 15291678 A JP15291678 A JP 15291678A JP 15291678 A JP15291678 A JP 15291678A JP S5578664 A JPS5578664 A JP S5578664A
Authority
JP
Japan
Prior art keywords
signal
output
decoder
memory
characters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15291678A
Other languages
Japanese (ja)
Inventor
Meiki Yahata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15291678A priority Critical patent/JPS5578664A/en
Publication of JPS5578664A publication Critical patent/JPS5578664A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the transmission time greatly by providing the memory memorizing previously the picture element pattern of the characters and then receiving the signal waves of the codes corresponding to the characters for reading and recording of the characters from the memory.
CONSTITUTION: Facsimile signal 1 is demodulated at demodulator 2, and then drawn into buffer memory 4 when the facsimile signal is code 3 showing the characters. While the output of dot counter 6 which is driven by clock 5 synchronizing with the recording velocity of the picture element plus line counter 7 which operates by using the output signal of counter 6 as the clock are supplied to decoder 8, and the output signal 9 is applied to multiplexer 10. Multiplexer 10 selects the word by signal 9 for the contents of memory 4 to supply it to decoder 12. Then the information to designate the address of ROM16 is delivered to output 13 of decoder 12. On the other hand, the output of counters 6 and 7 are supplied also to decoder 14, and the address designation information is delivered to output 15 of decoder 14. And picture signal 17 is obtained through memory 4 to be recorded through recording part 18.
COPYRIGHT: (C)1980,JPO&Japio
JP15291678A 1978-12-11 1978-12-11 Facsimile receiver Pending JPS5578664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15291678A JPS5578664A (en) 1978-12-11 1978-12-11 Facsimile receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15291678A JPS5578664A (en) 1978-12-11 1978-12-11 Facsimile receiver

Publications (1)

Publication Number Publication Date
JPS5578664A true JPS5578664A (en) 1980-06-13

Family

ID=15550941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15291678A Pending JPS5578664A (en) 1978-12-11 1978-12-11 Facsimile receiver

Country Status (1)

Country Link
JP (1) JPS5578664A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4825260A (en) * 1971-08-06 1973-04-02
JPS51107709A (en) * 1975-03-18 1976-09-24 Nippon Telegraph & Telephone

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4825260A (en) * 1971-08-06 1973-04-02
JPS51107709A (en) * 1975-03-18 1976-09-24 Nippon Telegraph & Telephone

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